receiver.v

fpga开发pci的verilog

module receiver(  
	rst,	
	qd,
	clk,
	r_ram_wdb,
	r_ram_wab,
	r_ram_wen,
	r_req,
	start_read
//	interrupt
	);	
					
/*** ports ***/
input	rst;
input	qd;
input	clk;

output	r_ram_wdb;
output	r_req;
output	[13:0]	r_ram_wab;
output	start_read;
output	r_ram_wen;

/***reg***/
reg	r_req ;  
//internal 
reg	[5:0]	STATE,next;
reg	[14:0]	r_ram_wab_reg;

//------------------------------------------------------------------
reg	qd_reg;
always @ (posedge clk)
	qd_reg <= qd ;

wire	r_ram_wdb = qd_reg;
//------------------------------------------------------------------
always @ (posedge clk or negedge rst)
	if(!rst)
	     STATE <= 6'b0;
	else
	     STATE <= next;
     
always @ (STATE or qd_reg or  r_ram_wab_reg)
begin
	next = 0;
	case(STATE)
	'd0:	if(qd_reg==1'b0)	next = 'd1;
		else	next = 'd0;
	'd1:	if(qd_reg==1'b0)	next = 'd2;
		else	next = 'd0;
	'd2:	if(qd_reg==1'b0)	next = 'd3;
		else	next = 'd0;
	'd3:	if(qd_reg==1'b1)	next = 'd4;
		else	next = 'd3;
		
	'd4:	if(qd_reg==1'b1)	next = 'd5;
		else	next = 'd1;
	'd5:	if(qd_reg==1'b0)	next = 'd6;
		else	next = 'd0;
	'd6:	if(qd_reg==1'b1)	next = 'd7;
		else	next = 'd2;        
	'd7:	if(qd_reg==1'b0)	next = 'd8;
		else	next = 'd0;  
		      
	'd8:	if(qd_reg==1'b1)	next = 'd9;
		else	next = 'd2;        
	'd9:	if(qd_reg==1'b1)	next = 'd10;
		else	next = 'd1;        
	'd10:	if(qd_reg==1'b0)	next = 'd11;
		else	next = 'd0;        
	'd11:	if(qd_reg==1'b0)	next = 'd12;
		else	next = 'd0; 
		       
	'd12:	if(qd_reg==1'b1)	next = 'd13;
		else	next = 'd2;        
	'd13:	if(qd_reg==1'b1)	next = 'd14;
		else	next = 'd1;        
	'd14:	if(qd_reg==1'b1)	next = 'd15;
		else	next = 'd1;        
	'd15:	if(qd_reg==1'b1)	next = 'd16;
		else	next = 'd1; 
		       
	'd16:	if(qd_reg==1'b1)	next = 'd17;
		else	next = 'd1;        
	'd17:	if(qd_reg==1'b1)	next = 'd18;
		else	next = 'd1;        
	'd18:	if(qd_reg==1'b1)	next = 'd19;
		else	next = 'd1;        
	'd19:	if(qd_reg==1'b1)	next = 'd20;
		else	next = 'd1; 
		       
	'd20:	if(qd_reg==1'b1)	next = 'd21;
		else	next = 'd1;        
	'd21:	if(qd_reg==1'b1)	next = 'd22;
		else	next = 'd1;        
	'd22:	if(qd_reg==1'b0)	next = 'd23;
		else	next = 'd0;        
	'd23:	if(qd_reg==1'b0)	next = 'd24;
		else	next = 'd0; 
		       
	'd24:	if(qd_reg==1'b0)	next = 'd25;
		else	next = 'd0;        
	'd25:	if(qd_reg==1'b0)	next = 'd26;
		else	next = 'd0;        
	'd26:	if(qd_reg==1'b0)	next = 'd27;
		else	next = 'd0;        
	'd27:	if(qd_reg==1'b1)	next = 'd28;
		else	next = 'd1; 
		       
	'd28:	if(qd_reg==1'b1)	next = 'd29;
		else	next = 'd1;
	'd29:	if(qd_reg==1'b1)	next = 'd30;
		else	next = 'd1;
	'd30:	if(qd_reg==1'b0)	next = 'd31;
		else	next = 'd0;
	'd31:	if(qd_reg==1'b1)	next = 'd32;
		else	next = 'd2;
	'd32:	if(r_ram_wab_reg=='d16383)	next = 'd33;//'d7135
		else	next = 'd32;
	'd33:	next = 'd0;
    endcase
end

//------------------------------------------------------------------
always @ (posedge clk or negedge rst)
	if(!rst)
	    r_ram_wab_reg <= 14'b0;
	else if(STATE == 'd32) begin
		if(r_ram_wab_reg == 'd16383)//'d7135
			r_ram_wab_reg <= 14'b0;
		else
			r_ram_wab_reg <= r_ram_wab_reg + 1'b1;
		end
	else
		r_ram_wab_reg <= 14'b0;

reg	r_ram_wab_hbit;
always @ (posedge clk or negedge rst)
	if(!rst)
	    r_ram_wab_hbit <= 1'b0;
	else if(STATE == 'd33)
		r_ram_wab_hbit <= ~r_ram_wab_hbit;
	else
		r_ram_wab_hbit <= r_ram_wab_hbit;	
	
wire	[15:0]	r_ram_wab = {r_ram_wab_hbit,r_ram_wab_reg};                                      
//------------------------------------------------------------------
wire	r_ram_wen = (STATE=='d32);
//------------------------------------------------------------------ 
always @ (posedge clk or negedge rst)
	if(!rst)
	    r_req <= 1'b0;
	else if(STATE=='d33)
	    r_req <= 1'b1;
	else
	    r_req <= 1'b0;
//------------------------------------------------------------------
reg	start_read;
always @ (posedge clk or negedge rst)
	if(!rst)
		start_read <= 1'b0;
	else if(STATE == 'd32)
		start_read <= 1'b1;
	else
		start_read <= 1'b0;
//------------------------------------------------------------------
	
endmodule