my.v

TMS3205402Verilog HDL源码

module my(
// DSP
	CPLD_RESET,

	MSTRB,
	IOSTRB,
	RW,

	DS,
	PS,
	IS,

	EA,
	A,
	A14,
	A15,
	D,

	INT3,

	FLASH_CE,
	FLASH_RD,
	FLASH_WE,
	DRAM_CE,
	DRAM_RD,
	DRAM_WE,
	PRAM_CE,
	PRAM_RD,
	PRAM_WE,
	
// IDE
	IDE0_CS0,
	IDE0_CS1,
	IDE1_CS0,
	IDE1_CS1,
	IDE_A,
	IDE_D,
	IDE_RD,
	IDE_WR,
//	IDE_RDY,
	LED0,
	LED1,

// USB
	PA0,
	PA1,
	SLOE,
	PA3,
	FIFOADR0,
	FIFOADR1,
	PKTEND,
	PA7,
	PB,
	PD,
	SLRD,
	SLWR,
	FLAGA,
	FLAGB,
	FLAGC,
	IFCLK,
	
//card
	CARD0_RST,
	CARD1_RST,
	CARD0_CLK,
	CARD1_CLK,
	CARD0_FLG,
	CARD1_FLG,
	CARD0_LED,
	CARD1_LED,
	CARD0_DATA,
	CARD1_DATA,
	GCLK
	);
	
	input	CPLD_RESET;
	input	MSTRB;
	input	IOSTRB;
	input	RW;
	input	DS;
	input	PS;
	input	IS;
	output	[19:15]	EA;
	input	[4:0]	A;
	input	A14;
	input	A15;
	inout	[15:0]	D;
	output	INT3;
	output	FLASH_CE;
	output	FLASH_RD;
	output	FLASH_WE;
	output	DRAM_CE;
	output	DRAM_RD;
	output	DRAM_WE;
	output	PRAM_CE;
	output	PRAM_RD;
	output	PRAM_WE;

	output	IDE0_CS0;
	output	IDE0_CS1;
	output	IDE1_CS0;
	output	IDE1_CS1;
	output	[3:0] IDE_A;
	inout	[15:0] IDE_D;
	output	IDE_RD;
	output	IDE_WR;
	output	LED0;
	output	LED1;
	
	input	PA0;
	input	PA1;
	output	SLOE;
	input	PA3;
	output	FIFOADR0;
	output	FIFOADR1;
	output	PKTEND;
	input	PA7;
	
	inout	[7:0] PB;
	inout	[7:0] PD;
	output	SLRD;
	output	SLWR;
	input	FLAGA;	// Programmable
	input	FLAGB;	// Full
	input	FLAGC;	// Empty
	input	IFCLK;

//CARD:
	output	CARD0_RST;
	output    CARD1_RST;
	output	CARD0_CLK;
	output	CARD1_CLK;
	input	CARD0_FLG;
	input	CARD1_FLG;
	output	CARD0_LED;
	output	CARD1_LED;
	inout	CARD0_DATA;
	inout	CARD1_DATA;

	input 	GCLK;

//CARD
	reg	CARD_NUM;
	

// DSP
	assign DRAM_CE = DS | (!EA[19]) ;
	assign DRAM_RD = MSTRB | (!RW) ;
	assign DRAM_WE = MSTRB | RW ;
	
	assign FLASH_CE = DS | EA[19]  ;  
	assign FLASH_RD = DRAM_RD ;
	assign FLASH_WE = DRAM_WE ;
	
	assign PRAM_CE = PS ;
	assign PRAM_RD = DRAM_RD ;
	assign PRAM_WE = DRAM_WE ;
	
	reg [15:0] DO;
	wire iord, iowr;
	
	assign iord = IOSTRB | (!RW) ;
	assign iowr = IOSTRB | RW ;


	wire ide_cs0,ide_cs1,reg_cs,usb_cs	;
	assign ide_cs0 = IS | A15 | A14;
	assign ide_cs1 = IS | A15 | (!A14);
	assign reg_cs = IS | (!A15) | (A14);
	assign usb_cs = IS | (!A15) | (!A14) ;

	wire reg_adder_cs,reg_ide_cs,reg_led_cs;
	assign reg_adder_cs = reg_cs |A[2] |  A[1]    |  A[0];	//8000
	assign reg_ide_cs =   reg_cs |A[2] |  A[1]    |(!A[0]);//8001
	assign reg_led_cs =   reg_cs |A[2] |(!A[1])   | (A[0]);//8002
	
	wire reg_card0_cs,reg_card1_cs,reg_card_num;
	assign reg_card0_cs = reg_cs |(!A[2]) |(A[1]) |(A[0])  |CARD_NUM    ;//8004
	assign reg_card1_cs = reg_cs |(!A[2]) |(A[1]) |(A[0])  |(!CARD_NUM) ;//8004
	assign reg_card_num = reg_cs |(!A[2]) |(A[1]) |(!A[0])              ;//8005

//EX_ADDER	
	reg	[19:15]	EA;
	always @(posedge iowr or negedge CPLD_RESET)
		begin
			if (CPLD_RESET == 0) 
				EA[19:15] = 5'b00000 ;
			else if ( !(reg_adder_cs) )
				EA[19:15] = D[4:0] ;
				
		end
 //LED
	assign LED1=PA7;

	reg LED0;
	always @(posedge iowr or negedge CPLD_RESET )
		begin
			if (CPLD_RESET == 0) 
				LED0 = 0 ;
			else if ( !(reg_led_cs) )
				LED0 = D[0] ;
		end
	
	 
// IDE
 	reg ide_num;
	always @(posedge iowr or negedge CPLD_RESET)
		begin
			if (CPLD_RESET == 0) 
				ide_num = 1'b1 ;
			else if ( !(reg_ide_cs) )
				ide_num = D[0] ;
		end
	assign	IDE0_CS0 = ide_num    | ide_cs0;
	assign	IDE0_CS1 = ide_num    | ide_cs1;
	assign	IDE1_CS0 = (!ide_num) | ide_cs0;
	assign	IDE1_CS1 = (!ide_num) | ide_cs1;
	
	wire	IDE_CS;
	assign	IDE_CS = ide_cs0 & ide_cs1;
	
	assign	IDE_RD = (IDE_CS) ? 1 : iord;
	assign	IDE_WR = (IDE_CS) ? 1 : iowr;
	
	assign	IDE_A = A[3:0];
	assign	IDE_D = (IDE_CS | iowr) ? 16'bz : D;

	
// USB
	assign INT3 = PA3;
	
	assign FIFOADR0 = A[0];
	assign FIFOADR1 = A[1];
	assign PKTEND=1;
		
	wire usb_state,usb_command,usb_data;
	assign usb_state = usb_cs | A[3] | A[2];
	assign usb_command = usb_cs | A[3] | (!A[2]);
	assign usb_data = usb_cs | (!A[3]) | A[2];
	wire bootloard_cs;
	assign bootloard_cs=usb_cs | (!A[4]) | (!A[3]) | (!A[2]) | (!A[1]) | (!A[0]);
//	reg SLOE, SLRD, SLWR;
	assign SLOE = usb_data | (!RW);
	assign SLRD = usb_data | iord;
	assign SLWR = usb_data | iowr;

	assign PB = (SLWR) ? 8'bz : D[7:0];
		

//CARD_CLOCK: 48MHz/16	=>	3MHz
	wire clk357, CARD0_CLK_ENA,  CARD1_CLK_ENA ;
     reg [3:0] COUNT;
 
	always @(posedge GCLK or negedge CPLD_RESET)
		begin
		   if (CPLD_RESET==0)
		      COUNT = 3'b0;
		   else
		      COUNT = COUNT + 1;
 		end
	assign clk357=COUNT[3];


//CARD_NUM
	always @(posedge iowr or negedge CPLD_RESET)
		begin
			if (CPLD_RESET == 0) 
				CARD_NUM=0 ;
			else if ( !(reg_card_num) )
				CARD_NUM = D[0] ;
				
		end

//CARD0
	reg	[3:0]	CARD0;	
	always @(posedge iowr or negedge CPLD_RESET)
		begin
			if (CPLD_RESET == 0) 
				CARD0[3:0] = 4'b0000 ;
			else if ( !(reg_card0_cs) )
				CARD0[3:0] = D[3:0] ;
				
		end

	assign CARD0_DATA	=(CARD0[0]) ? 1'bz : 0;
	assign CARD0_LED	=	CARD0[1];
	assign CARD0_CLK_ENA=	CARD0[2];
	assign CARD0_RST	=	CARD0[3];
//CARD1
	reg	[3:0]	CARD1;	
	always @(posedge iowr or negedge CPLD_RESET)
		begin
			if (CPLD_RESET == 0) 
				CARD1[3:0] = 4'b0000 ;
			else if ( !(reg_card1_cs) )
				CARD1[3:0] = D[3:0] ;
				
		end
	assign CARD1_DATA	=(CARD1[0]) ? 1'bz : 0;
	assign CARD1_LED	=	CARD1[1];
	assign CARD1_CLK_ENA=	CARD1[2];
	assign CARD1_RST	=	CARD1[3];

	assign CARD0_CLK = (CARD0_CLK_ENA)	? clk357 : 0;
	assign CARD1_CLK = (CARD1_CLK_ENA)	? clk357 : 0;


// Read Out
	always @(IDE_CS or reg_adder_cs or usb_state or usb_command or usb_data or IDE_D or EA or FLAGB or FLAGC or PA0 or PA1 or PB)
		begin
			if (!IDE_CS)
				DO = IDE_D;
			else if	(!reg_adder_cs )
				DO = {11'bz, EA[19:15]};
			else if (!usb_state )
				DO = {14'bz, FLAGC, FLAGB};
			else if (!usb_command )
				DO = {14'bz, PA1, PA0};
			else if (!usb_data )
				DO = {8'bz, PB[7:0]};

			else if (!reg_card0_cs )
				DO = {14'bz, CARD0_FLG, CARD0_DATA};
			else if (!reg_card1_cs )
				DO = {14'bz, CARD1_FLG,CARD1_DATA};
			else if (!bootloard_cs)
				DO = 16'b1000000000000000;
			else
				DO = 16'bz;
		end
	
	assign	D = (iord) ? 16'bz : DO;
	
endmodule