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V 的代码
fdiv.v
module fdiv(
clk,
f200hz,
f60hz,
f1hz
);
output f200hz,f60hz,f1hz;
input clk; //1KHz input
reg f200hz,f60hz,f1hz;
integer CNT1=0,CNT2=0,CNT3=0;
always @(posedge clk)
be
alarmclock.v
module alarmclock(
clk_200hz,
EN,
SW1,SW2,
hour1,hour0,
minute1,minute0,
second1,second0,
alarm,
alarmclock_disp_select);
output
timeset.v
module timeset(
TimeSet_EN,
SW1,SW2,
hour1,hour0,
minute1,minute0,
second1,second0,
hour_set1,hour_set0,
minute_set1,minute_set0,
second_set1,se
alarmclock.v
module alarmclock(
clk_200hz,
EN,
SW1,SW2,
hour1,hour0,
minute1,minute0,
second1,second0,
alarm,
alarmclock_disp_select);
output
timeset.v
module timeset(
TimeSet_EN,
SW1,SW2,
hour1,hour0,
minute1,minute0,
second1,second0,
hour_set1,hour_set0,
minute_set1,minute_set0,
second_set1,se
fdiv.v
module fdiv(
clk,
f200hz,
f60hz,
f1hz
);
output f200hz,f60hz,f1hz;
input clk; //1KHz input
reg f200hz,f60hz,f1hz;
integer CNT1=0,CNT2=0,CNT3=0;
always @(posedge clk)
be
maincontrol.v
module maincontrol(
SW3,
Timepiece_EN,
TimeSet_EN,
Stopwatch_EN,
Alarmclock_EN,
Date_EN,
DateSet_EN);
output Timepiece_EN,TimeSet_EN,Stopwatch_EN,Alarmcloc
stopwatch.v
module stopwatch(clk1,clk2,EN,F_out);
output F_out;
input EN;
input clk1,clk2;
reg F_out;
always @(EN,clk1,clk2)
begin
case(EN)
1'b0: F_out
setdate.v
module setdate(EN2,SW1,SW2,disp_drive,month_set1,month_set0,day_set1,day_set0);
output [1:0] disp_drive;
output [3:0] month_set1,month_set0,day_set1,day_set0;
input EN2; //EN2为手动设置日期使能
input S
main.v
module main(
SW3,
SW2,
SW1,
Clock,
alarm,
disp_data,
disp_select
);
input SW3;
input SW2;
input SW1;
input Clock;
output alarm;
output [6:0] disp_data;
output [5:0] disp_select