alarmclock.v

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

module alarmclock(
                  clk_200hz,
				  EN,
				  SW1,SW2,
				  hour1,hour0,
				  minute1,minute0,
				  second1,second0,
				  alarm,
				  alarmclock_disp_select);

output alarm;
output [5:0] alarmclock_disp_select;
input  EN,SW1,SW2,clk_200hz;
input  [3:0] hour1,hour0,minute1,minute0,second1,second0;

reg [5:0] alarmclock_disp_select;
reg alarm;
reg [3:0] hour_set1,hour_set0;      //存放设置的小时
reg [3:0] minute_set1,minute_set0;  //存放设置的分
reg [3:0] second_set1,second_set0;  //存放设置的秒

reg [2:0] disp_drive;              //设置闹钟时间时，数码管显示的动态位选择

//闹钟一直工作（设置的闹钟时间与当前时间比较）
always
begin
  if((hour_set1 == hour1)&&(hour_set0 == hour0)
     &&(minute_set1 == minute1)&&(minute_set0 == minute0)
     &&(second_set1 == second1)&&(second_set0 == second0))
	alarm <= 1'b1;
  else
	alarm <= 1'b0;
end


//闹钟设置中，按SW1一次，将移位一次，显示当前设置位
always @(posedge SW1)
begin
  if(EN == 1'b1)
	begin
	  if(disp_drive != 3'b101)
		disp_drive <= disp_drive + 3'b1;
	  else
	    disp_drive <= 3'b000;
	end
end

//当前位的闹钟数字设置，按SW2一次，数字增加1
always @(posedge SW2)
begin
  case(disp_drive)
	//
	3'b000: begin
			   //disp_select <= 6'b100000;  
			   if(hour_set1 < 4'b0010) 
				   hour_set1 <= hour_set1 + 4'b1;
               else
			       hour_set1 <= 4'b0;
			end
	//
	3'b001: begin
			  //disp_select <= 6'b010000; 
			   if((hour_set1 < 4'b0010)&&(hour_set0 < 4'b1001)) 
				   hour_set0 <= hour_set0 + 4'b1;
			   else if((hour_set1 == 4'b0010)&&(hour_set0 < 4'b0100))
				   hour_set0 <= hour_set0 + 4'b1;
			   else
				   hour_set0 <= 4'b0;
			end
	//
	3'b010: begin
			   //disp_select <= 6'b001000; 
			   if(minute_set1 < 4'b0101) 
			   	   minute_set1 <= minute_set1 + 4'b1;
			   else
			   	   minute_set1 <= 4'b0;
			end
	//
	3'b011: begin
			   //disp_select <= 6'b000100; 
			   if(minute_set0 < 4'b1001) 
				   minute_set0 <= minute_set0 + 4'b1;
			   else
				   minute_set0 <= 4'b0;
			end
	//
	3'b100: begin
			  //disp_select <= 6'b000010; 
			   if(second_set1 < 4'b0101) 
				   second_set1 <= second_set1 + 4'b1;
			   else
				   second_set1 <= 4'b0;
			end
	//
	3'b101: begin
			   //disp_select <= 6'b000001; 
			   if(second_set0 < 4'b1001) 
				   second_set0 <= second_set0 + 4'b1;
			   else
			       second_set0 <= 4'b0;
			end
	default: begin
			 end
  endcase
end

//闪烁显示
always @(posedge clk_200hz)
begin
  case(disp_drive)
	//
	3'b000:  alarmclock_disp_select <= 6'b100000;
	//
	3'b001:  alarmclock_disp_select <= 6'b010000;
	//
	3'b010:  alarmclock_disp_select <= 6'b001000;
	//
	3'b011:  alarmclock_disp_select <= 6'b000100;
	//
	3'b100:  alarmclock_disp_select <= 6'b000010;
	//
	3'b101:  alarmclock_disp_select <= 6'b000001;
	default: alarmclock_disp_select <= 6'b000000;
  endcase  
end

endmodule