main.v

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

module main(
	SW3,
	SW2,
	SW1,
	Clock,
	alarm,
	disp_data,
	disp_select
);

input	SW3;
input	SW2;
input	SW1;
input	Clock;
output	alarm;
output	[6:0] disp_data;
output	[5:0] disp_select;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_41;
wire	SYNTHESIZED_WIRE_42;
wire	SYNTHESIZED_WIRE_43;
wire	SYNTHESIZED_WIRE_44;
wire	[3:0] SYNTHESIZED_WIRE_45;
wire	[3:0] SYNTHESIZED_WIRE_46;
wire	[3:0] SYNTHESIZED_WIRE_47;
wire	[3:0] SYNTHESIZED_WIRE_48;
wire	[3:0] SYNTHESIZED_WIRE_49;
wire	[3:0] SYNTHESIZED_WIRE_50;
wire	SYNTHESIZED_WIRE_51;
wire	SYNTHESIZED_WIRE_12;
wire	SYNTHESIZED_WIRE_13;
wire	SYNTHESIZED_WIRE_52;
wire	SYNTHESIZED_WIRE_16;
wire	SYNTHESIZED_WIRE_53;
wire	[2:0] SYNTHESIZED_WIRE_21;
wire	[5:0] SYNTHESIZED_WIRE_28;
wire	[5:0] SYNTHESIZED_WIRE_29;
wire	[3:0] SYNTHESIZED_WIRE_30;
wire	[3:0] SYNTHESIZED_WIRE_31;
wire	[3:0] SYNTHESIZED_WIRE_36;
wire	[3:0] SYNTHESIZED_WIRE_37;
wire	[5:0] SYNTHESIZED_WIRE_40;





time_auto_and_set	b2v_inst1(.CLK(SYNTHESIZED_WIRE_0),
.Timepiece_EN(SYNTHESIZED_WIRE_41),.TimeSet_EN(SYNTHESIZED_WIRE_42),.SW1(SW1),.SW2(SW2),.Day_EN(SYNTHESIZED_WIRE_16),.hour_0(SYNTHESIZED_WIRE_45),.hour_1(SYNTHESIZED_WIRE_46),.minute_0(SYNTHESIZED_WIRE_47),.minute_1(SYNTHESIZED_WIRE_48),.second_0(SYNTHESIZED_WIRE_49),.second_1(SYNTHESIZED_WIRE_50),.TimeSet_disp_drive(SYNTHESIZED_WIRE_21));

alarmclock	b2v_inst11(.EN(SYNTHESIZED_WIRE_43),
.SW1(SW1),.SW2(SW2),.clk_200hz(SYNTHESIZED_WIRE_44),.hour0(SYNTHESIZED_WIRE_45),.hour1(SYNTHESIZED_WIRE_46),.minute0(SYNTHESIZED_WIRE_47),.minute1(SYNTHESIZED_WIRE_48),.second0(SYNTHESIZED_WIRE_49),.second1(SYNTHESIZED_WIRE_50),.alarm(alarm),.alarmclock_disp_select(SYNTHESIZED_WIRE_28));

stopwatch	b2v_inst2(.EN(SYNTHESIZED_WIRE_51),
.clk1(SYNTHESIZED_WIRE_12),.clk2(SYNTHESIZED_WIRE_13),.F_out(SYNTHESIZED_WIRE_0));

maincontrol	b2v_inst3(.SW3(SW3),
.Timepiece_EN(SYNTHESIZED_WIRE_41),.TimeSet_EN(SYNTHESIZED_WIRE_42),.Stopwatch_EN(SYNTHESIZED_WIRE_51),.Alarmclock_EN(SYNTHESIZED_WIRE_43),.Date_EN(SYNTHESIZED_WIRE_52),.DateSet_EN(SYNTHESIZED_WIRE_53));

date_main	b2v_inst4(.Date_EN(SYNTHESIZED_WIRE_52),
.date_disp_clk(SYNTHESIZED_WIRE_44),.day_EN(SYNTHESIZED_WIRE_16),.Date_Set_EN(SYNTHESIZED_WIRE_53),.SW1(SW1),.SW2(SW2),.day0(SYNTHESIZED_WIRE_30),.day1(SYNTHESIZED_WIRE_31),.Disp_select_date(SYNTHESIZED_WIRE_29),.month0(SYNTHESIZED_WIRE_36),.month1(SYNTHESIZED_WIRE_37));

fdiv	b2v_inst5(.clk(Clock),
.f200hz(SYNTHESIZED_WIRE_44),.f60hz(SYNTHESIZED_WIRE_13),.f1hz(SYNTHESIZED_WIRE_12));

time_disp_select	b2v_inst6(.clk_1khz(Clock),
.clk_200hz(SYNTHESIZED_WIRE_44),.Time_EN(SYNTHESIZED_WIRE_41),.TimeSet_EN(SYNTHESIZED_WIRE_42),.timeset_disp_drive(SYNTHESIZED_WIRE_21),.time_disp_select(SYNTHESIZED_WIRE_40));

disp_data_mux	b2v_inst8(.Timepiece_EN(SYNTHESIZED_WIRE_41),
.TimeSet_EN(SYNTHESIZED_WIRE_42),.Stopwatch_EN(SYNTHESIZED_WIRE_51),.Alarmclock_EN(SYNTHESIZED_WIRE_43),.Date_EN(SYNTHESIZED_WIRE_52),.DateSet_EN(SYNTHESIZED_WIRE_53),.alarmclock_disp_select(SYNTHESIZED_WIRE_28),.date_disp_select(SYNTHESIZED_WIRE_29),.day0(SYNTHESIZED_WIRE_30),.day1(SYNTHESIZED_WIRE_31),.hour0(SYNTHESIZED_WIRE_45),.hour1(SYNTHESIZED_WIRE_46),.minute0(SYNTHESIZED_WIRE_47),.minute1(SYNTHESIZED_WIRE_48),.month0(SYNTHESIZED_WIRE_36),.month1(SYNTHESIZED_WIRE_37),.second0(SYNTHESIZED_WIRE_49),.second1(SYNTHESIZED_WIRE_50),.time_disp_select(SYNTHESIZED_WIRE_40),.disp_data(disp_data),.disp_select(disp_select));


endmodule