trafficlight.v

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验

module traffic(clk,snCar,ewCar,
		snRed,snYellow,snGreen,
		ewRed,ewYellow,ewGreen);
input snCar, ewCar,clk;
output reg snRed;
output reg snYellow;
output reg snGreen;
output reg ewRed;
output reg ewYellow;
output reg ewGreen;

reg [5:0] state;
reg [15:0] timer1;
reg [7:0] timer2;
reg time1Up,time2Up;
reg enableTime1,enableTime2;


parameter TIME1NUM=2000, TIME2NUM=200;
parameter EWGREEN=5'b00000, EWGREENWAIT=5'b00001;
parameter EWYELLOW=5'b00010;
parameter SNGREEN=5'b00100, SNGREENWAIT=5'b01000; 
parameter SNYELLOW=5'b10000;

always @(posedge clk)
	if (enableTime1) 
		if (timer1==TIME1NUM) time1Up<=1;
		else 	timer1<=timer1+1;
	else 
	begin
		timer1<=0;
		time1Up<=0;
	end
always @(posedge clk)
	if (enableTime2) 
		if (timer2==TIME2NUM) time2Up<=1;
		else 	timer2<=timer2+1;
	else 
	begin
		timer2<=0;
		time2Up<=0;
	end
always @(state)
	case (state)
		EWGREEN: 	
			if (time1Up)	state<=EWGREENWAIT;
		EWGREENWAIT: 	
			if (snCar)		state<=EWYELLOW;
		EWYELLOW:	
			if (time2Up)	state<=SNGREEN;
		SNGREEN: 	
			if (time1Up)	state<=SNGREENWAIT;
		SNGREENWAIT:	
			if (ewCar)		state<=SNYELLOW;
		SNYELLOW:	
			if (time2Up)	state<=EWGREEN;
		default:	state<=EWGREEN;
	endcase

always @(posedge clk)
	case (state)
		EWGREEN:
			 	begin
					enableTime1<=1;
					enableTime2<=0;
					ewGreen<=1;
					ewYellow<=0;
					ewRed<=0;
					snGreen<=0;
					snYellow<=0;
					snRed<=1;
				end
		EWGREENWAIT:
				enableTime1<=0;
		EWYELLOW:
				begin
					enableTime2<=1;
					ewGreen<=0;
					ewYellow<=1;
					ewRed<=0;
					snGreen<=0;
					snYellow<=0;
					snRed<=1;
				end
		SNGREEN: 	
				begin
					enableTime2<=0;
					enableTime1<=1;
					ewGreen<=0;
					ewYellow<=0;
					ewRed<=1;
					snGreen<=1;
					snYellow<=0;
					snRed<=0;
				end
		SNGREENWAIT:
				enableTime1<=0;
		SNYELLOW:
				begin
					enableTime2<=1;	
					ewGreen<=0;
					ewYellow<=0;
					ewRed<=1;
					snGreen<=0;
					snYellow<=1;
					snRed<=0;
				end
		endcase
endmodule