autoled.v

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验

module LEDauto(display,rst,displayclk,scan);
	input rst,displayclk;
	output reg [7:0]display;
	output reg [3:0]scan;

	reg [3:0] singlenum[3:0];

	parameter ZERO = 8'b11111100,ONE = 8'b01100000, TWO = 8'b11011010;
	parameter THREE = 8'b11110010, FOUR =8'b01100110;
	parameter FIVE = 8'b10110110, SIX = 8'b10111110, SEVEN =8'b11100000;
	parameter EIGHT = 8'b11111110, NINE = 8'b11110110, BLANK = 8'b00000000;


	always @(posedge displayclk or negedge rst)
	begin
	   if(!rst)
	   begin
	   		singlenum[0] = 0;
	   		singlenum[1] = 1;
	   		singlenum[2] = 2;
	   		singlenum[3] = 3;
	   		scan = 4'b0001;
	   end
	   else
	   begin
	   	   case(scan)
				4'b0001: scan = 4'b0010;
				4'b0010: scan = 4'b0100;
				4'b0100: scan = 4'b1000;
				4'b1000: scan = 4'b0001;
				default: scan = 4'b0001;
	   		endcase
		end
	end
	always @(scan)
	begin
	    if(scan == 4'b0001)
	    begin
	    	case(singlenum[0])
	    		1: display = ONE;
				2: display = TWO;
				3: display = THREE;
				4: display = FOUR;
				5: display = FIVE;
				6: display = SIX;
				7: display = SEVEN;
				8: display = EIGHT;
				9: display = NINE;
				0: display = ZERO;
				default: display = ZERO;
			endcase
		end
		else if(scan == 4'b0010)
	    begin
	    	case(singlenum[1])
	    		1: display = ONE;
				2: display = TWO;
				3: display = THREE;
				4: display = FOUR;
				5: display = FIVE;
				6: display = SIX;
				7: display = SEVEN;
				8: display = EIGHT;
				9: display = NINE;
				0: display = ZERO;
				default: display = ZERO;
		 	endcase
		end
	    else if(scan == 4'b0100)
	    begin
	    	case(singlenum[2])
	    		1: display = ONE;
				2: display = TWO;
				3: display = THREE;
				4: display = FOUR;
				5: display = FIVE;
				6: display = SIX;
				7: display = SEVEN;
				8: display = EIGHT;
				9: display = NINE;
				0: display = ZERO;
 				default: display = ZERO;
		 	endcase
		end

	    else if (scan == 4'b1000)
	    begin
	    	case(singlenum[3])
	    		1: display = ONE;
				2: display = TWO;
				3: display = THREE;
				4: display = FOUR;
				5: display = FIVE;
				6: display = SIX;
				7: display = SEVEN;
				8: display = EIGHT;
				9: display = NINE;
				0: display = ZERO;
 				default: display = ZERO;
		 	endcase
		end
	end	
endmodule