基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
标签： fpga vga显示 verilog quartus
上传时间： 2021-12-19
上传用户：kingwide
FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明，使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz时钟 input rst_n //复位信号，低电平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO写数据wire wr_en; //FIFO写使能wire rd_en; //FIFO读使能wire[15:0] r_data; //FIFO读数据wire full; //FIFO满信号 wire empty; //FIFO空信号 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///产生FIFO写入的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 开始写FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO满 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///产生FIFO读的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO满, 开始读FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上传时间： 2021-12-19
上传用户：20125101110
CHAPTER 1: THE OP AMP CHAPTER 2: OTHER LINEAR CIRCUITS CHAPTER 3: SENSORS CHAPTER 4: RF/IF CIRCUITS CHAPTER 5: FUNDAMENTALS OF SAMPLED DATA SYSTEMS CHAPTER 6: CONVERTERS CHAPTER 7: DATA CONVERTER SUPPORT CIRCUITS CHAPTER 8: ANALOG FILTERS CHAPTER 9: POWER MANAGEMENT CHAPTER 10: PASSIVE COMPONENTS CHAPTER 11: OVERVOLTAGE EFFECTS ON ANALOG INTEGRATED CIRCUITS CHAPTER 12: PRINTED CIRCUIT BOARD (PCB) DESIGN ISSUES CHAPTER 13: DESIGN DEVELOPMENT TOOLS
上传时间： 2021-12-21
上传用户：wangshoupeng199
FPGA Verilog HDL设计温度传感器ds18b20温度读取并通过lcd1620和8位LED数码管显示的QUARTUS II 12.0工程文件，包括完整的设计文件.V源码，可以做为你的学习及设计参考。module ds18b20lcd1602display ( Clk, Rst, DQ, //18B20数据端口 Txd, //串口发送端口 LCD_Data, //lcd LCD_RS, LCD_RW, LCD_En, SMData, //数码管段码 SMCom //数码管位码 );input Rst,Clk;output Txd,LCD_RS,LCD_En,LCD_RW;inout DQ;output[7:0] LCD_Data;output[7:0] SMData;output[3:0] SMCom;wire DataReady;//测温完成信号wire [15:0] MeasureResult;//DS18B20测温结果reg [15:0] Temperature;//产生LCD的位码和段码LCD1602Display Gen_LCD(.resetin(Rst),.clkin(Clk),.Data16bIn(Temperature),.lcd_data(LCD_Data),.lcd_rs(LCD_RS),.lcd_rw(LCD_RW),.lcd_e(LCD_En)/*,.SMCom(SMCom)*/);//DS18B20测温和发送 DS18B20 TmpMeasureAndTx(.Rst(Rst),.Clk(Clk),.DQ(DQ),.Txd(Txd),.FinishFlag(DataReady),.Data16b(MeasureResult));//产生数码管的位码和段码SMDisplay Gen_SM(.Rst(Rst),.
标签： fpga verilog hdl 温度传感器 ds18b20 lcd1620 数码显示
上传时间： 2022-01-30
上传用户：
spi 通信的master部分使用的verilog语言实现，可以做为你的设计参考。module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata); input rstb,clk,mlb,start; input [7:0] tdat; //transmit data input [1:0] cdiv; //clock divider input din; output reg ss; output reg sck; output reg dout; output reg done; output reg [7:0] rdata; //received dataparameter idle=2'b00; parameter send=2'b10; parameter finish=2'b11; reg [1:0] cur,nxt; reg [7:0] treg,rreg; reg [3:0] nbit; reg [4:0] mid,cnt; reg shift,clr;
上传时间： 2022-02-03
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verilog实现I2C通信的slave模块源码状态机设位计可做I2C接口的仿真模型//`timescale 1ns/1psmodule I2C_slv (input [6:0] slv_id,input RESET,input scl_i, //I2C clkinput sda_i, //I2C data ininput [7:0] I2C_RDDATA,////////////////////////output reg sda_o, //I2C data outoutput reg reg_w, //reg write enable pulse (1T of scl_i)output reg [7:0] I2C_ADDR,output reg [7:0] I2C_DATA); parameter ST_ADDR = 4'd0; parameter ST_ACK = 4'd1; parameter ST_WDATA1 = 4'd2; parameter ST_WACK1 = 4'd3; parameter ST_WDATA2 = 4'd4; parameter ST_WACK2 = 4'd5; parameter ST_WDATA3 = 4'd6; parameter ST_WACK3 = 4'd7; parameter ST_RDATA1 = 4'd8; parameter ST_RACK1 = 4'd9; parameter ST_IDLE = 4'd15;//---------------------------------------------------------------------------// Signal Declaration//--------------------------------------------------------------------------- reg i2c_start_n, i2c_stop_n; //wire RESET_scl; wire i2c_stp_n, i2c_RESET; reg [3:0] i2c_cs, i2c_ns; reg [3:0] cnt_bit; reg [7:0] d_vec; reg i2c_rd, i2c_ack; reg [7:0] I2C_RDDATA_latch;
上传时间： 2022-02-03
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Ansoft公司的Maww2D/3D是一个功能强大、结果精确、易于使用的二维/三维电磁场有限元分析软件。它包括电场、静磁场、涡流场、瞬态场和温度场分析模块，可以用来分析电机、传感器、变压器、永磁设备、激励器等电磁装置的静态、稳态、瞬态、正常工况和故障工况的特性。它所包含的自上而下执行的用户界面、领先的自适应网格剖分技术及用户定义材料库等特点，使得它在易用性上遥遥领先。它具有高性能矩阵求解器和多CUP处理能力，提供了最快的求解速度。静磁场求解器（Magnetostatic）用于分析由恒定电流、永磁体及外部激磁引起的磁场，是用于激励器、传感器、电机及永磁体等。该模块可自动计算磁场力、转矩、电感和储能用于求解某些涉及到运动和任意波形的电压、电流源激励的设备，可获得精确的预测性能特性。该模块能同时求解磁场电路及运动等强耦合的方程，从而得到电机的相关运行性能●涡流场求解器（Eddy Current用于分析受涡流、集肤效应、邻近效应影响的系统。它求解的频率范围可以从θ到数百兆赫兹，能够自动计算损耗、铁损、力、转矩、电感与储能。允许用户设置多项可变设计量，如位置、形状、源及频率等。可自动计算数千种情况的物理问题分析，而整个过程不许用户干预。在绘制曲线模型时，系统默认的是将封闭后的曲线自动生成面，如果用户不想让其自动生成面，可以在绘制曲线模型前，点击菜单栏中的 Tools/Options/Modeler Options项更改绘图设置。材料库的管理更加方便和直观，新版软件的材料库主要由两类组成，一是系统自带材料库的2D和3D有限元计算常用材料库除此外还有 RMxprt电机设计模块用的电机材料库。二是用户材料库，可以将常用的且系统材料库中没有的材料单独输岀成用户材料库，库名称可自行命名，在使用前须将用户材料库装载进软件中
上传时间： 2022-03-17
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电子书-RTL Design Style Guide for Verilog HDL540页A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
标签： RTL verilog hdl
上传时间： 2022-03-21
上传用户：canderile
研究一种智能扫地机器人。从硬件系统控制模块设计到主要技术调试进行了较详细的阐述。以STM32单片机为控制核心与电机驱动、红外线路径识别模块等相互协调应用。进行电路搭建和程序编写。实现了智能扫地机器人红外线避障和自动扫地功能,其清扫面积能达到约70%,清扫率约60%,很大程度受到自身机械机构的限制,后期将对小车的机械结构进行完善。This paper studies an intelligent sweeping robot.From the hardware system control module design to the main technical debugging are described in detail.STM32 MCU is used as the control core to coordinate with motor drive and infrared path recognition module.Conduct circuit building and programming.The functions of infrared obstacle avoidance and automatic sweeping of intelligent sweeping robot are realized.Its cleaning area can reach about 70%and the cleaning rate is about 60%.Because it is limited by its own mechanical mechanism to a great extent,the mechanical structure of the car will be improved in the later stage.
标签： 扫地机器人
上传时间： 2022-03-26
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设计了农业温湿度智能控制系统,该系统采用DHT11温湿度传感器作为温湿度采集模块,单片机选用AT89C52代替并调用Virtual terminal模拟串口通信,LCD1604液晶显示器实时显示温湿度,实现了温湿度的测量、显示,可自动控制加热、降温、加湿、通风,实现温湿度控制以及超限报警处理,并利用Proteus与Keil进行实际电路的仿真。试验表明,该系统实现了可靠的温湿度监控。We described the design of an intelligent control system of agriculture temperature and humidity.The system uses DHT11 temperature and humidity sensor as the temperature and humidity acquisition module.The SCM adopts AT89C52 to replace and call the virtual terminal for simulating serial communication.LCD1604 displays temperature and humidity in real time,which implements the measurement and display of temperature and humidity.The system is able to automatically control heating,cooling,humidification and ventilation,to achieve temperature and humidity control and over-limit alarm processing.The system also uses Proteus and Keil for actual circuit simulation.The experiment shows that the system is capable of reliable temperature and humidity monitoring.
上传时间： 2022-03-26
上传用户：aben
