Wherever possible the overall technique used for this series will be "definition by example" withgeneric formulae included for use in other applications. To make stability analysis easy we will usemore than one tool from our toolbox with data sheet information, tricks, rules-of-thumb, SPICESimulation, and real-world testing all accelerating our design of stable operational amplifier (op amp)circuits. These tools are specifically targeted at voltage feedback op amps with unity-gain bandwidths<20 MHz, although many of the techniques are applicable to any voltage feedback op amp. 20 MHz ischosen because as we increase to higher bandwidth circuits there are other major factors in closing theloop: such as parasitic capacitances on PCBs, parasitic inductances in capacitors, parasitic inductancesand capacitances in resistors, etc. Most of the rules-of-thumb and techniques were developed not justfrom theory but from the actual building of real-world circuits with op amps <20 MHz.
标签： 运算放大器
上传时间： 2021-11-01
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基于TMS320F2812 光伏并网发电模拟装置PROTEL设计原理图+PCB+软件源码+WORD论文文档,硬件采用2层板设计，PROTEL99SE 设计的工程文件，包括完整的原理图和PCB文件，可以做为你的学习设计参考。 摘要：本文实现了一个基于TMS320F2812 DSP芯片的光伏并网发电模拟装置，采用直流稳压源和滑动变阻器来模拟光伏电池。通过TMS320F2812 DSP芯片ADC模块实时采样模拟电网电压的正弦参考信号、光伏电池输出电压、负载电压电流反馈信号等。经过数据处理后，用PWM模块产生实时的SPWM 波，控制MOSFET逆变全桥输出正弦波。本文用PI控制算法实现了输出信号对给定模拟电网电压的正弦参考信号的频率和相位跟踪，用恒定电压法实现了光伏电池最大功率点跟踪（MPPT），从而达到模拟并网的效果。另外本装置还实现了光伏电池输出欠压、负载过流保护功能以及光伏电池输出欠压、过流保护自恢复功能、声光报警功能、孤岛效应的检测、保护与自恢复功能。系统测试结果表明本设计完全满定设计要求。关键词：光伏并网，MPPT，DSP Photovoltaic Grid-connected generation simulator Zhangyuxin，Tantiancheng，Xiewuyang(College of Electrical Engineering, Chongqing University)Abstract: This paper presents a photovoltaic grid-connected generation simulator which is based on TMS320F2812 DSP, with a DC voltage source and a variable resistor to simulate the characteristic of photovoltaic cells. We use the internal AD converter to real-time sampling the referenced grid voltage signal, outputting voltage of photovoltaic, feedback outputting voltage and current signal. The PWM module generates SVPWM according to the calculation of the real-time sampling data, to control the full MOSFET inverter bridge output sine wave. We realized that the output voltage of the simulator can track the frequency and phase of the referenced grid voltage with PI regulation, and the maximum photovoltaic power tracking with constant voltage regulation, thereby achieved the purpose of grid-connected simulation. Additionally, this device has the over-voltage and over-current protection, audible and visual alarm, islanding detecting and protection, and it can recover automatically. The testing shows that our design is feasible.Keywords: Photovoltaic Grid-connected，MPPT，DSP 目录引言 11. 方案论证 11.1. 总体介绍 11.2. 光伏电池模拟装置 11.3. DC-AC逆变桥 11.4. MOSFET驱动电路方案 21.5. 逆变电路的变频控制方案 22. 理论分析与计算 22.1. SPWM产生 22.1.1. 规则采样法 22.1.2. SPWM 脉冲的计算公式 32.1.3. SPWM 脉冲计算公式中的参数计算 32.1.4. TMS320F2812 DSP控制器的事件管理单元 42.1.5. 软件设计方法 62.2. MPPT的控制方法与参数计算 72.3. 同频、同相的控制方法和参数计算 8
标签： tms320f2812 光伏 并网发电 模拟 protel pcb
上传时间： 2021-11-02
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使用说明 ：1， 解压文件。2，打开PADS 软件， 依次点选 tools basicscripts ,basicscripts,load file, 选取PcbPartLocation.BAS 文件， 点选 RUN 。大功告成（ 注意PADS 位号字体相同）
标签： pads
上传时间： 2021-11-04
上传用户：XuVshu
The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
上传时间： 2021-11-09
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CH340C+RT9013+MINI USB接口板 AD设计硬件原理图+PCB文件,ALTIUM设计的2层板设计，包括完整的原理图和PCB文件，主要器件如下：Library Component Count : 12Name Description----------------------------------------------------------------------------------------------------CAP CapacitorCC2640EM CC2630 ModuleCH340 CH340 USB 2 UARTCON11 Connector 11pinsCON12 Connector 12pinsCON3X2 Connector 5*2LED LEDRES ResistorRT9013 RT9013 3.3VSWITCH switch 6*6USB1 USB ConnectorsXDS110-Lte XDS110-Lite Target Interface
上传时间： 2021-11-24
上传用户：canderile
STM32L475开发板PDF原理图+AD集成3D封装库+主要器件技术手册，集成封装库型号列表如下：Library Component Count : 44Name Description----------------------------------------------------------------------------------------------------ANT-2.4G ANT,2.4G,PCB天线ATK-TEST-1*4-2.54mm 测试点ATK_MODULE 单排母,1*6,2.54mmBEEP 3.3V有源蜂鸣器BUTTON_DIP3 拨动开关SS-12F44C-0402-SMD C-0603-SMD C-CAP-SMD-220uF/10V C-CEP-220uF/16V D-1N4148 Header-1*3-2.54mm 单排针-2.54mmHeader-2*10-2.54mm 双排针-2.54mmHeader-2*2-2.54mm 双排针-2.54mmHeader-2*3-2.54mm 双排针-2.54mmHeader-2*4-2.54mm 双排座-2.54mmIR-LED 1206红外发射管（侧）IR-LF0038GKLL-1 红外接收管SMDJ-MICRO-USB-5S Micro USB 5.9有柱脚长1.25加长针L-0420-4.7uH 电感,4.7uH,3ALCD-TFT-H13TS38A LCD,TFT,1.3'240*240,禹龙LED-0603-RED 发光二极管-红色LED-RGB-1615-0603 RGB,共阳,1615,0603MIC-6022 MICMotor-SMD 电机,SMDPhone-3-M 耳机座,三节R-0402-SMD 贴片电阻R-0805-SMD 贴片电阻RT9193-3.3S-KEY-SMD-324225 KEY,SMD,324225S8050-SMD SD-MICRO-TF SD,MICRO,TFU-AHT10 Sensor,温湿度传感器U-AP3216C Sensor.光照/距离U-AP6181 WIFI Module,SDIOU-ES8388 AUDIO,2-ch DAC,2-ch ADCU-ICM-20608 三轴陀螺仪/三轴加速度计,U-L9110S 电机驱动,800mAU-RT9013-3.3 LDO,500mAU-STM32F103C8T6 U-STM32L475VET6 MCU,LQFP100,512K FLASH,128K RAMU-W25Q128 SPI FLASH,16MY-12M-SMD 晶振 - 12M贴片Y-3215-32.768K XTAL,3215,32.768KY-3215-8M XTAL,3215,8MHz
上传时间： 2021-12-15
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include<reg52.h> #define uint unsigned int #define uchar unsigned char uint temp,aa,wang,qian,bai,shi,ge; sbit dula=P2^6; sbit wela=P2^7; uchar code table[]={ 0x3f,0x06,0x5b,0x4f, 0x66,0x6d,0x7d,0x07, 0x7f,0x6f,0x77,0x7c, 0x39,0x5e,0x79,0x71}; void display( uint wang,uint qian,uint bai,uint shi,uint ge); void delay(uint z); void init(); void main() { init();//初始化子程序 while(1) { if(aa==20) { aa=0; temp++; if(temp==99999) { temp=0; } wang=temp/10000; qian=(temp-wang*10000)/1000; bai=(temp-wang*10000-qian*1000)/100; shi=(temp-wang*10000-qian*1000-bai*100)/10; ge=temp%10; } display(wang,qian, bai,shi,ge); } } void delay(uint z) { uint x,y; for(x=z;x>0;x--) for(y=110;y>0;y--); } void display(uint wang,uint qian,uint bai,uint shi,uint ge) { dula=1; P0=table[wang]; dula=0; P0=0xff; wela=1; P0=0xfe; wela=0; delay(1); dula=1; P0=table[qian]; dula=0; P0=0xff; wela=1; P0=0xfd; wela=0; delay(1); dula=1; P0=table[bai]; dula=0; P0=0xff; wela=1; P0=0xfb; wela=0; delay(1); dula=1; P0=table[shi]; dula=0; P0=0xff; wela=1; P0=0xf7; wela=0; delay(1); dula=1; P0=table[ge]; dula=0; P0=0xff; wela=1; P0=0xef; wela=0; delay(1); } void init() { wela=0; dula=0; temp=0; TMOD=0x01; TH0=(65536-50000)/256; TL0=(65536-50000)%256; EA=1; ET0=1; TR0=1; } void timer0() interrupt 1 { TH0=(65536-50000)/256; TL0=(65536-50000)%256; aa++; } include<reg52.h> #define uint unsigned int #define uchar unsigned char uint temp,aa,wang,qian,bai,shi,ge; sbit dula=P2^6; sbit wela=P2^7; uchar code table[]={ 0x3f,0x06,0x5b,0x4f, 0x66,0x6d,0x7d,0x07, 0x7f,0x6f,0x77,0x7c, 0x39,0x5e,0x79,0x71}; void display( uint wang,uint qian,uint bai,uint shi,uint ge); void delay(uint z); void init(); void main() { init();//初始化子程序 while(1) { if(aa==20) { aa=0; temp++; if(temp==99999) { temp=0; } wang=temp/10000; qian=(temp-wang*10000)/1000; bai=(temp-wang*10000-qian*1000)/100; shi=(temp-wang*10000-qian*1000-bai*100)/10; ge=temp%10; } display(wang,qian, bai,shi,ge); } } void delay(uint z) { uint x,y; for(x=z;x>0;x--) for(y=110;y>0;y--); } void display(uint wang,uint qian,uint bai,uint shi,uint ge) { dula=1; P0=table[wang]; dula=0; P0=0xff; wela=1; P0=0xfe; wela=0; delay(1); dula=1; P0=table[qian]; dula=0; P0=0xff; wela=1; P0=0xfd; wela=0; delay(1); dula=1; P0=table[bai]; dula=0; P0=0xff; wela=1; P0=0xfb; wela=0; delay(1); dula=1; P0=table[shi]; dula=0; P0=0xff; wela=1; P0=0xf7; wela=0; delay(1); dula=1; P0=table[ge]; dula=0; P0=0xff; wela=1; P0=0xef; wela=0; delay(1); } void init() { wela=0; dula=0; temp=0; TMOD=0x01; TH0=(65536-50000)/256; TL0=(65536-50000)%256; EA=1; ET0=1; TR0=1; } void timer0() interrupt 1 { TH0=(65536-50000)/256; TL0=(65536-50000)%256; aa++; } include<reg52.h> #define uint unsigned int #define uchar unsigned char uint temp,aa,wang,qian,bai,shi,ge; sbit dula=P2^6; sbit wela=P2^7; uchar code table[]={ 0x3f,0x06,0x5b,0x4f, 0x66,0x6d,0x7d,0x07, 0x7f,0x6f,0x77,0x7c, 0x39,0x5e,0x79,0x71}; void display( uint wang,uint qian,uint bai,uint shi,uint ge); void delay(uint z); void init(); void main() { init();//初始化子程序 while(1) { if(aa==20) { aa=0; temp++; if(temp==99999) { temp=0; } wang=temp/10000; qian=(temp-wang*10000)/1000; bai=(temp-wang*10000-qian*1000)/100; shi=(temp-wang*10000-qian*1000-bai*100)/10; ge=temp%10; } display(wang,qian, bai,shi,ge); } } void delay(uint z) { uint x,y; for(x=z;x>0;x--) for(y=110;y>0;y--); } void display(uint wang,uint qian,uint bai,uint shi,uint ge) { dula=1; P0=table[wang]; dula=0; P0=0xff; wela=1; P0=0xfe; wela=0; delay(1); dula=1; P0=table[qian]; dula=0; P0=0xff; wela=1; P0=0xfd; wela=0; delay(1); dula=1; P0=table[bai]; dula=0; P0=0xff; wela=1; P0=0xfb; wela=0; delay(1); dula=1; P0=table[shi]; dula=0; P0=0xff; wela=1; P0=0xf7; wela=0; delay(1); dula=1; P0=table[ge]; dula=0; P0=0xff; wela=1; P0=0xef; wela=0; delay(1); } void init() { wela=0; dula=0; temp=0; TMOD=0x01; TH0=(65536-50000)/256; TL0=(65536-50000)%256; EA=1; ET0=1; TR0=1; } void timer0() interrupt 1 { TH0=(65536-50000)/256; TL0=(65536-50000)%256; aa++; }
标签： 矩阵式键盘
上传时间： 2021-12-18
上传用户：2590813506
FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上传时间： 2021-12-18
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基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中，再从ROM 中把转换后的数据读取出来显示到 VGA 上，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上传时间： 2021-12-18
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基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
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