vhdl proc_common_v2_00_a "E:\EDK8.1/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" vhdl proc_co…
Active+HDL 源代码
汇集 Active+HDL 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
// (Version 1.00 :: 10-Mar-1999 :: Harutoshi Yoshida) // Dlg_ComStt.cpp : 僀儞僾儕儊儞僥乕僔儑儞 僼傽僀儖 // #include "stdafx.h" #include…
// (Version 1.00 :: 10-Mar-1999 :: Harutoshi Yoshida) /*=================================================================== 恔搙忣…
%RRI_PROGRESS_UI Use rri_progress_status to render the progress bar % % Usage: rri_progress_ui('initialize') or % rr…
%READ_EEG_FORMAT First, choose a vendor name of the EEG system, from which % the EEG data was acquired. Second, choose a file f…
#ifndef GET_HANDLER #define GET_HANDLER Handler *getHandler(char *nameOfHandler) { HandlerNode* hn = (HandlerNode*) rtsys->h…
#ifndef CREATE_HANDLER #define CREATE_HANDLER bool ttCreateInterruptHandler(char *name, double priority, double (*codeFcn)(int, v…
#ifndef CREATE_PERIODIC_TASK #define CREATE_PERIODIC_TASK #include "createtask.cpp" bool ttCreatePeriodicTask(char *name, double…
#ifndef INIT_KERNEL #define INIT_KERNEL // Creates an interrupt handler to simulate context switches Handler *createCShandler(voi…
AHDL2BLF ABEL-HDL Processor PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.