Active+HDL 源代码

function fm_comp(flag) % FM_COMP define settings and operations of the GUI % for creating new components % % FM_COMP(FLAG)…

function fm_theme(command) % FM_THEME set PSAT theme properties % % FM_THEME(COMMAND) % COMMAND specific setting command % %s…

function fm_bar(command) % FM_BAR draws PSAT status bar % % FM_BAR(COMMAND) % %see also FM_MAIN % %Author: Federico Milano %Dat…

Warning (10236): Verilog HDL Implicit Net warning at vga_colors.v(82): created implicit net for "lineWire"

AHDL2BLF ABEL-HDL Processor PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.

function edgedemo(action, varargin) % 子函数： % InitializeEDGEDEMO - 初始化图像、控件、轴 % ComputeEdgeMap - 调用edge.m计算原始图像的边缘图 % Sele…

必须有hdl.var和cds.lib。 LDV4，要手工写vcd_trace LDV5能够自动添加所有端口和信号，但信号或端口在声明时应有字符串参数作为名字，否则ncsc会用默认的名字signalxxx或portxxx，无法识别。

AHDL2BLF ABEL-HDL Processor PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.

AHDL2BLF ABEL-HDL Processor PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.

AHDL2BLF ABEL-HDL Processor PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.