代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/448916/7522451

vhd scan.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity scan is port(indata:in std_logic_vector(31 downto 0); clk:in std_logic; control:out integer
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vhd triangle1.vhd

Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity triangle1 is port( clk: in std_logic; data: out std_logic_vector(7 downto 0)); end entity triangle1; arc
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vhd add.vhd

Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity add is port( clk: in std_logic;--两个控制信号 clk1: in std_logic; add: out std_logic_vector(7 downto 0)); end
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vhd triangle.vhd

Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity triangle is port( clk: in std_logic; data: out std_logic_vector(7 downto 0)); end entity triangle; arch
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txt vhdl源代码.txt

以下为正弦波的VHDL语言编程源程序： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sin4 is port(clk4:in std_logic; dd4:out integer range 255
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vhd 4bit_alu.vhd

--4 bit alu library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; -- dis_out connects to 7 seg
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vhd fbitaddr.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --library UNISIM; --use UNISIM.VComponents.all; entity fbitaddr is Port ( a4 :
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vhd alu_2bit.vhd

--4 bit alu library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; -- dis_out connects to 7 seg
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www.eeworm.com/read/447996/7542408

vhd 4bit_alu.vhd

--4 bit alu library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; -- dis_out connects to 7 seg
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www.eeworm.com/read/447996/7542464

vhd fbitaddr.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --library UNISIM; --use UNISIM.VComponents.all; entity fbitaddr is Port ( a4 :
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