4bit_alu.vhd

this program performs the functonality of 4 bit alu

--4 bit alu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;

-- dis_out connects to 7 seg disp lines, ain and bin are 4 bit switch
-- i/ps, sout represents the result of logic oprn routede to leds, sel
-- i/p to select different oprns in arithmetic and logical modes, m i/p
-- to select arith or the logical mode, cin is carray i/p with cout being
-- a carry o/p, oen1,2,3,4 are 7 seg led enable lines

entity alu_4bit is
		 Port(dis_out : out std_logic_vector(7 downto 0);
                	ain : in std_logic_vector(3 downto 0);
               	bin : in std_logic_vector(3 downto 0);
			    sout : out std_logic_vector(3 downto 0);
			      sel: in std_logic;
			       m : in std_logic;
			     clk1: in std_logic;
                	cin : in std_logic;
			     cout: out std_logic;
                   oen1 : out std_logic;
			      ce : in std_logic;
                   oen2 : out std_logic;
			    oen3 : out std_logic;
			    oen4 : out std_logic);
end alu_4bit;

architecture Behavioral of alu_4bit is
-- locally used signals
    	 signal dtemp:std_logic_vector(3 downto 0);
	 signal stemp: std_logic_vector(3 downto 0);
      signal tempdis: std_logic_vector(7 downto 0);
 	 signal bclk:std_logic;
	 signal bbclk:std_logic;
  	 signal soen1:std_logic;
	 signal soen2: std_logic;
	 signal temp_out: std_logic_vector(7 downto 0);
	 signal tempcout:std_logic;
	 signal tempsout:std_logic_vector(3 downto 0);
--sub component declaration of test count
	 component testcnt
	 	port( clk : in std_logic;
			  rst: in std_logic;
			 one :out std_logic);
		end component;
--sub component declaration of d flipflop
		component dflip
      port ( clk   : in    std_logic; 
             ben2  : out   std_logic; 
             en1   : out   std_logic);
   	end component;
--sub component declaration of 4 bit adder
		component fbitaddr
		port(a4 : in std_logic_vector(3 downto 0);
           	b4 : in std_logic_vector(3 downto 0);
           	s4 : out std_logic_vector(3 downto 0);
           	ci : in std_logic;
           	co : out std_logic);
end component;
--component istantiation
begin
-- port mapping of test count
	u1:testcnt 
	port map( clk => clk1,rst => ce,one => bclk);
-- port mapping of test count
	u2:testcnt 
	port map	(clk => bclk,rst =>ce,one => bbclk);
-- port map of d flip flop
	u4:dflip
      port map (clk=>bbclk, ben2=>soen2, en1=>soen1);

-- port map of 4 bit full adder   
	u5:fbitaddr 
	port map	(a4 =>ain, b4 => bin, s4 =>tempsout, ci =>cin, co=>tempcout); 	

	oen3 <= '1';
	oen4 <= '1';
   	cout <= tempcout;
  	sout <= stemp;
	 
pp1: process (soen1,soen2)
 begin
		  	oen1 <= soen1;
			oen2 <= soen2;

-- 7 seg 1(left) used to display carry
			if soen1 = '0' then
					-- if carry is present indicate it on the disp else not			
					if tempcout = '1' then
					 	dis_out <= "10111111";
					else
						dis_out <= "11111111";
					end if;
			
			end if;
-- 7 seg 2(right) to display the result of arithmetic oprn				
			if soen2 = '0' then
				dis_out <= tempdis;
			end if;
end process pp1;

pp2: process(tempsout,cin,sel,temp_out,m,ce)
begin
-- if m == 0 arithmetic oprns	
	if m = '0' then
-- if select==0 then only one i/p will be handled
		if sel = '0' then
			if cin = '1' then
			  	dtemp <= ain + '1';
			  	tempdis <= temp_out;
		  end if;
--if select==1 then both the i/ps are handled
		else if sel = '1' then
					if cin = '0' then
						dtemp <=  ain + bin;
						tempdis <=  temp_out;
					end if;
	  		end if;
		end if;
	else
-- else if m == 1 logical oprns
      -- if select ==0, and operation
		if sel = '0' then
			stemp <= ain and bin;
		end if;
      --if select ==1 then or oprn
		if sel = '1' then
			stemp <= ain or bin;
	   end if;
	end if;

end process pp2;
--to display the result of arithmetic operation on 7 seg display
pp3:process(dtemp)
 begin
 		if (dtemp = "0000") then
			temp_out <= "11000000";
		else if (dtemp = "0001")then
			temp_out <= "11111001";
		else if (dtemp = "0010")then
			temp_out <= "10100100";
		else if (dtemp = "0011") then
			temp_out <= "10110000";
		else if (dtemp = "0100") then
			temp_out <= "10011001";
		else if (dtemp = "0101") then
			temp_out <= "10010010";
		else if (dtemp = "0110") then
			temp_out <=  "10000010";
		else if (dtemp = "0111") then
			temp_out <= "11111000";
		else if (dtemp = "1000") then
			temp_out <= "10000000";
		else if (dtemp = "1001") then
			temp_out <=	"11111000";
		else if (dtemp = "1010") then
			temp_out <= "10000010";
		else if (dtemp = "1011") then
			temp_out <= "10010010";
		else if(dtemp = "1100") then
			temp_out <= "10011001";
		else if (dtemp = "1101") then
			temp_out <= "10110000";
		else if(dtemp = "1110") then
			temp_out <= "10100100";
		else if (dtemp <= "1111") then
			temp_out <= "11111001";
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
		end if;
end process pp3;
end Behavioral;