testcnt.vhd

来自「this program performs the functonality o」· VHDL 代码 · 共 34 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity testcnt is
    Port ( clk : in std_logic;
           rst : in std_logic;
         	  one: out std_logic);
end testcnt;

architecture Behavioral of testcnt is
	  signal cnt : std_logic_vector(4 downto 0):="00000";
	  	  signal temp: std_logic:='0';
begin
  one <= temp;
process(clk,rst)
begin
	if rst = '1' then
		cnt <= "00000"; 
	else
		if clk'event and clk = '1' then
			if cnt < "11000" then
				cnt <= cnt + '1';
			else
				temp <= not temp;
				cnt <= "00000";
			end if;
		end if;
	end if;
end process;	
				
end Behavioral;