scan.vhd

来自「本程序完整的实现了数字频率计的常用功能。并对通常数字频率计的常见问题进行了改进。」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity scan is
  port(indata:in std_logic_vector(31 downto 0);
       clk:in std_logic;
       control:out integer range 0 to 7;
       data:out std_logic_vector(3 downto 0));
end entity;
architecture art of scan is
  signal count:integer range 0 to 7;
  begin
    process(clk)
    begin
      if(rising_edge(clk)) then
        if (count=7) then
          count<=0;
        else count<=count+1;
        end if;
      end if;
    end process;
    
    process(count)
    begin
      case count is
         when 0=>data<=indata(3 downto 0);
         when 1=>data<=indata(7 downto 4);
         when 2=>data<=indata(11 downto 8);
         when 3=>data<=indata(15 downto 12);
         when 4=>data<=indata(19 downto 16);
         when 5=>data<=indata(23 downto 20);
         when 6=>data<=indata(27 downto 24);
         when 7=>data<=indata(31 downto 28);
         when others=>data<=indata(3 downto 0);
      end case;
    end process;
    control<=count;
end art;