fbitaddr.vhd

this program performs the functonality of 4 bit alu

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--library UNISIM;
--use UNISIM.VComponents.all;

entity fbitaddr is
    Port ( a4 : in std_logic_vector(3 downto 0);
           b4 : in std_logic_vector(3 downto 0);
           s4 : out std_logic_vector(3 downto 0);
           ci : in std_logic;
           co : out std_logic);
end fbitaddr;

architecture Behavioral of fbitaddr is
		signal c1,c2,c3,c4: std_logic;
	component fulladdr
	port(   cin : in std_logic;
           cout : out std_logic;
           a : in std_logic;
           b : in std_logic;
           s : out std_logic
			  );
end component;

begin
u1: fulladdr
   port map( cin => ci,	a => a4(0),	b => b4(0),	s => s4(0),	cout => c1);

u2: fulladdr
   port map( cin => c1,	a=> a4(1), b => b4(1), s => s4(1), cout => c2);

u3: fulladdr
   port map( cin => c2,	a=> a4(2), b => b4(2), s => s4(2), cout => c3);

u4: fulladdr
   port map( cin => c3,	a=> a4(3), b => b4(3), s => s4(3), cout => c4);

process(c4)
begin
		co <= c4;
end process;
end Behavioral;