add.vhd

来自「关于CPLD程序」· VHDL 代码 · 共 27 行

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity add is port(
	clk:	in std_logic;--两个控制信号
	clk1:   in std_logic;
add:	out std_logic_vector(7 downto 0));
end entity add;

architecture depict of add is
	signal tmp:	std_logic_vector(7 downto 0);
begin
	process(clk)
	begin
		if(rising_edge(clk))then
			case clk1 is
                 when '0'=>tmp<=tmp+2;--ts <= ts + 1;

                 when '1'=>tmp<=tmp+1; --ts <= ts + 1;
                 when  others=>tmp<=tmp; --ts <= ts + 1;      
          end case;
	end if;
end process;
	add<=tmp;
end depict;