vhdl源代码.txt

基于可编程逻辑器件实现任意波形发生器VHDL源代码

以下为正弦波的VHDL语言编程源程序：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sin4 is
port(clk4:in std_logic;
dd4:out integer range 255 downto 0);---输出范围为
0到255
end;
architecture dacc of sin4 is
signal q: integer range 63 downto 0;
begin
process(clk4)
begin
if (clk4'event and clk4='1') then
q<=q+1;
end if;
end process;
process(q)
begin
case q is
when 00=>dd4<=255;
when 01=>dd4<=254;
when 02=>dd4<=253;
when 03=>dd4<=250;
when 04=>dd4<=245;
when 05=>dd4<=240;
when 06=>dd4<=234;
when 07=>dd4<=226;
when 08=>dd4<=218;
when 09=>dd4<=208;
when 10=>dd4<=198;
when 11=>dd4<=188;
when 12=>dd4<=176;
when 13=>dd4<=165;
when 14=>dd4<=152;
when 15=>dd4<=140;
when 16=>dd4<=128;
when 17=>dd4<=115;
when 18=>dd4<=103;
when 19=>dd4<=90;
when 20=>dd4<=79;
when 21=>dd4<=67;
when 22=>dd4<=57;
when 23=>dd4<=47;
when 24=>dd4<=37;
when 25=>dd4<=29;
when 26=>dd4<=21;
when 27=>dd4<=15;
when 28=>dd4<=10;
when 29=>dd4<=5;
when 30=>dd4<=2;
when 31=>dd4<=1;
when 32=>dd4<=0;
when 33=>dd4<=1;
when 34=>dd4<=2;
when 35=>dd4<=5;
when 36=>dd4<=10;
when 37=>dd4<=15;
when 38=>dd4<=21;
when 39=>dd4<=29;
when 40=>dd4<=37;
when 41=>dd4<=47;
when 42=>dd4<=57;
when 43=>dd4<=67;
when 44=>dd4<=79;
when 45=>dd4<=90;
when 46=>dd4<=103;
when 47=>dd4<=115;
when 48=>dd4<=128;
when 49=>dd4<=140;
when 50=>dd4<=165;
when 51=>dd4<=176;
when 52=>dd4<=188;
when 53=>dd4<=198;
when 54=>dd4<=208;
when 55=>dd4<=218;
when 56=>dd4<=226;
when 57=>dd4<=234;
when 58=>dd4<=240;
when 59=>dd4<=245;
when 60=>dd4<=250;
when 61=>dd4<=253;
when 62=>dd4<=254;
when 63=>dd4<=255;
when others=>null;
end case;
end process;
end architecture;

三角波的设计

由于三角是由线形增加和线形递减的两个直线构成，所以可以直接使用VHDL语言编程来实现三角波，当线形自加到最高点时，由控制语句控制其自减，直到减到最低点时再重复之前过程，从而实现三角波。以下是采用VHDL语言的三角波编程源程序：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sanj is
port(clk3:in std_logic;
dd3:out std_logic_vector(7 downto 0));
end sanj;
architecture art of sanj is
signal b:std_logic;
signal c:std_logic_vector(7 downto 0);
begin
process(clk3)
begin
if (clk3'event and clk3='1') then
if(b='0') then
c<=c+1;
if(c=250) then
b<='1';
end if;
elsif(b='1') then
c<=c-1;
if(c=1) then
b<='0';
end if;
end if;
dd3<=c;
end if;
end process;
end art;

锯齿波的设计

对于锯齿波的采样，也可以完全用VHDL语言来实现，当加到所要求的最高点时，由控制语句使其返回0点重复以前过程，从而实现锯齿波。另外，设置一个控制按键，来控制输出上升锯齿波形或下降锯齿波形，如图5、图6所示。

图5 （略）

图6 （略）

以下为锯齿波VHDL语言编程源程序：

library ieee;
use ieee.std_logic.1164.all;
entity jvchi2 is
potr(clk2,up_down: in std_logic;
dd2:buffer integer range 255 downto 0);
end;
architecture one of jvchi2 is
signal d,temp:integer range 255 downto 0;
begin
process(clk2)
begin
if(clk2'event and clk2='1') then
if temp<198 then temp<=temp+2;
else temp<=0;
end if;
end if;
end process;
process(temp,up_down)
begin
if up_down='0' then d<=temp;
else d<=198-temp;
end if;
end process;
dd2<=d;
end;

方波的设计

由于时钟脉冲输出即是方波波形，所以对方波的设计可以简化为直接输出时钟脉冲信号。但是，在本设计中方波与其他三个波形要同步且要经过D/A转换，所以还需把时钟脉冲变成8位输出才可以经由D/A转换输出，具体过程可以由以下程序实现：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fang2 is
port(
clk1 : in std_logic;
dd1 : buffer integer range 255 downto 0);
end;
architecture dacc of fang2 is
signal q: integer range 1 downto 0;
begin
process(clk1)
begin
if (clk1'event and clk1='1') then
q<=q+1;
end if;
end process;
process(q)
begin
case q is
when 0=>dd1<=255;
when 1=>dd1<=0;
when others=>null;
end case;
end process;
end architecture;

波形选择与控制的设计

在前面已经分别设计了四种基础波形，现在需做的是如何将四种波形融合在一起成为一个整体，并使它们能按操作输出所需波形，这就需要波形选择与控制模块。这个功能由时钟脉冲输入选择模块完成。当选择了一种情况时，对应的波形模块输入时钟脉冲，并输出波形数据，其他三个则始终输入为0，不能输出波形。但是，其他波形始终有0信号输入，也能产生数据，会对波形产生干扰。因此，需要输出波形选择模块来选择有用的波形，隔离干扰数据。为了达到时钟脉冲选择与输出波形选择的统一，同时也为了消除延迟，在输出波形选择模块与时钟脉冲选择模块里控制开关是同一组。这样当输入一种控制数据时，输出的波形也就是所需的波形。这样设计，可以减少按键的数量，节省资源降低错误几率。下面是设计的连线总图及时钟脉冲选择与输出波形选择程序：

图 （略）

时钟脉冲输入选择器VHDL语言编程源程序：

library ieee;
use ieee.std_logic_1164.all;
entity mux42 is
port(clk : in std_logic;
s: in std_logic_vector(1 downto 0);
z1,z2,z3,z4: out std_logic);
end entity mux42;
architecture art of mux42 is
begin
process(s)
begin
case s is
when "00"=>z1<=clk;
when "01"=>z2<=clk;
when "10"=>z3<=clk;
when "11"=>z4<=clk;
when others=>z1<=null;
z2<=null;
z3<=null;
z4<=null;
end case;
end process;
end art;

输出波形选择器VHDL语言编程源程序：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity yand1 is
p ort(dd1,dd2,dd3,dd4 : in std_logic_vector (7 downto 0);
s: in std_logic_vector(1 downto 0);
y: : out std_logic_vector (7 downto 0));
end entity yand1;
architecture art of yand1 is
begin
process(s)
begin
case s is
when "00"=>y<=dd4;
when "01"=>y<=dd3;
when "10"=>y<=dd2;
when "11"=>y<=dd1;
when others=>null;
end case;
end process;
end architecture art;