triangle1.vhd

来自「关于CPLD程序」· VHDL 代码 · 共 32 行

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity triangle1 is port(
	clk:	in std_logic;
	data:	out std_logic_vector(7 downto 0));
end entity triangle1;

architecture depict of triangle1 is
	signal tmp:	std_logic_vector(7 downto 0);
begin
	process(clk)
		variable cnt: integer range 1 to 128;
	begin
		if(rising_edge(clk))then
			if(cnt = 128) then
				cnt := 1;
			else
				cnt := cnt + 1;
			end if;

 			if(cnt < 65) then
				tmp <= tmp + 1;
			else
				tmp <= tmp - 1;
			end if;
		end if;
	end process;
	data<=tmp;
end depict;