triangle.vhd

来自「关于CPLD程序」· VHDL 代码 · 共 21 行

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity triangle is port( 
	clk:	in std_logic;
	data:	out std_logic_vector(7 downto 0));
end entity triangle;

architecture depict of triangle is
	signal tmp:	std_logic_vector(7 downto 0);
begin
	process(clk)
	begin
		if(rising_edge(clk))then
			tmp<=tmp+1;
		end if;
	end process;
	data<=tmp;
end depict;