代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/166544/10016694
vhd convert.vhd
Library ieee;
USE IEEE.std_logic_1164.all;
Entity convert IS
port(a:in std_logic_vector(3 downto 0);
sel2,sel4:in std_logic;
b:out std_logic_vector(7 downto 0));
End convert;
architect
www.eeworm.com/read/166544/10016698
vhd bell.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bell is
port(
q1,q2,q3,q4:in std_logic_vector(3 downto 0);
ena,reset: in std_logic;
clk: in std_logic;
www.eeworm.com/read/166544/10016702
vhd dataselect.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY dataselect IS
PORT(
sel : IN STD_LOGIC_VECTOR(3 downto 0);
p0,p1,p2,p3,p4
www.eeworm.com/read/166544/10016713
vhd comclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY comclk IS
PORT(
sel: IN STD_LOGIC_VECTOR(2 downto 0);
clk:in std_logic;
www.eeworm.com/read/166544/10016722
vhd ymdhms.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ymdhms is
port(
setn:std_logic_vector(5 downto 0);
ena,clk:in std_logic;
cosecond: out std_logic;
y
www.eeworm.com/read/362114/10017650
vhd usbf_pd.vhd
--file usbf_pd.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity usbf_pd is
generic
(
usbf_t_pid_out : std_logic_vector
www.eeworm.com/read/301737/10047981
vhd rs232_t.vhd
--the rs232 send module
--include one clk and one send component
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
entity rs232_t is --send and pll1的物理连接
p
www.eeworm.com/read/361043/10068055
vhd pcore.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.all;
--synopsys translate_on
entity pcore is
port (
clk: i
www.eeworm.com/read/360965/10070862
vhd ofdm_kernel_tx_tb.vhd
-- ================================================================================
-- (c) 2007 Altera Corporation. All rights reserved.
-- Altera products are protected under numerous U.S. and fore
www.eeworm.com/read/360965/10070878
vhd cp_mem.vhd
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: cp_mem.vhd