bell.vhd

电子打铃器 在max plus 2 下编译通过

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bell is
port(
	q1,q2,q3,q4:in std_logic_vector(3 downto 0);
	ena,reset: in std_logic;	
	clk: in std_logic;
	co: out std_logic;
	
	data1,data2,data3,data4:out std_logic_vector(3 downto 0)
	);
end bell;

architecture rtl of bell is
component bellcnt10
port(
	clk: in std_logic;
	reset,en: in std_logic;	
	co: out std_logic;
	data1: out std_logic_vector(3 downto 0)
	);
end component;
    signal p1,p2,p3,p4: std_logic_vector(3 downto 0);
	signal temp1,temp2,temp3,temp4: std_logic_vector(3 downto 0);
	signal temp5: std_logic_vector(1 downto 0);
	signal co1,co2,co3,co4,reset1,reset2,treset1,treset2,ena1,ena2,ro1,ro2:std_logic;
begin
--	p1<=q1-1;
--	p2<=q2;
--	p3<=q3-1;
--	p4<=q4;
	ena1<=temp5(0);
	ena2<=not temp5(0);
	reset1<=reset or treset1;
	reset2<=reset or treset2;
	u1:bellcnt10
	port map (clk,reset1,ena1,co1,temp1);
	u2:bellcnt10
	port map (clk,reset1,co1,co2,temp2);
	u3:bellcnt10
	port map (clk,reset2,ena2,co3,temp3);
	u4:bellcnt10
	port map (clk,reset2,co3,co4,temp4);

    data1<=q1+1;
	data2<=q2;
	data3<=q3+1;
	data4<=q4;

	ro1<='1' when (((temp1=q1 and temp2=q2) or (temp3=q3 and temp4=q4)) and ena='1') else '0';
	treset1<='1' when(temp3=q3 and temp4=q4) else'0';
	treset2<='1' when(temp1=q1 and temp2=q2) else'0';
	process(clk)
		begin
			if clk'event and clk='1' then
				ro2<=ro1;
		    end if;
	end process;
	process(ro2)
		begin
			if ro2'event and ro2='1' then
				temp5<=temp5+1;
			end if;
	end process;
	co<=ro2;
end rtl;