convert.vhd

电子打铃器 在max plus 2 下编译通过

Library ieee;
USE IEEE.std_logic_1164.all;
Entity convert IS
port(a:in std_logic_vector(3 downto 0);
	 sel2,sel4:in std_logic;
     b:out std_logic_vector(7 downto 0));
End convert;

architecture ct of convert is
signal tempb:std_logic_vector(6 downto 0);
begin
 
tempb<=
	 "0111111" when a="0000"
  else  
     "0000110" when a="0001"
  else 
     "1011011" when a="0010"
  else 
     "1001111" when a="0011" 
  else 
     "1100110" when a="0100"
  else
     "1101101" when a="0101"
  else  
     "1111101" when a="0110"
  else
     "0000111" when a="0111"
  else
     "1111111" when a="1000"
  else
     "1101111" when a="1001"
  else
     "1110111" when a="1010"
  else
     "1111100" when a="1011"
  else
     "0111001" when a="1100"
  else
     "1011110" when a="1101"
  else
     "1111001" when a="1110"
  else
     "1110001" when a="1111"
  else
     "0000000";

 b<=(sel2 or sel4)&tempb;
end ct;