dataselect.vhd

电子打铃器 在max plus 2 下编译通过

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY dataselect IS
	PORT(
		sel	: IN	STD_LOGIC_VECTOR(3 downto 0);
		p0,p1,p2,p3,p4,p5: IN STD_LOGIC_VECTOR(3 downto 0);
		a0,a1,a2,a3,a4,a5: IN STD_LOGIC_VECTOR(3 downto 0);
		b0,b1,b2,b3,b4,b5: IN	STD_LOGIC_VECTOR(3 downto 0);
		h0,h1,h2,h3,h4,h5: IN std_logic_vector(3 downto 0);
		q0,q1,q2,q3,q4,q5	: OUT	STD_LOGIC_VECTOR(3 downto 0)
				
		);
END dataselect;

ARCHITECTURE a OF dataselect IS
	SIGNAL r0,r1,r2,r3,r4,r5 : STD_LOGIC_VECTOR(3 downto 0);
	SIGNAL c0,c1,c2,c3,c4,c5: STD_LOGIC_VECTOR(3 downto 0);
	SIGNAL d0,d1,d2,d3,d4,d5: STD_LOGIC_VECTOR(3 downto 0);
	SIGNAL m0,m1,m2,m3,m4,m5: std_logic_vector(3 downto 0);
BEGIN
	r0<=p0;
	r1<=p1;
	r2<=p2;
	r3<=p3;
	r4<=p4;
	r5<=p5;
	c0<=a0;
	c1<=a1;
	c2<=a2;
	c3<=a3;
	c4<=a4;
	c5<=a5;
	d0<=b0;
	d1<=b1;
	d2<=b2;
	d3<=b3;
	d4<=b4;
	d5<=b5;
	m0<=h0;
	m1<=h1;
	m2<=h2;
	m3<=h3;
	m4<=h4;
	m5<=h5;
	PROCESS (sel)
		BEGIN
			CASE sel IS
				WHEN "0010" =>
				    q0<=r0;
					q1<=r1;
					q2<=r2;
					q3<=r3;
					q4<=r4;
					q5<=r5;
				WHEN "0001" =>
				    q0<=c0;
					q1<=c1;
					q2<=c2;
					q3<=c3;
					q4<=c4;
					q5<=c5;
				WHEN "0100"=>
					q0<=d0;
					q1<=d1;
					q2<=d2;
					q3<=d3;
					q4<=d4;
					q5<=d5;

				WHEN OTHERS =>
				    q0<=m0;
					q1<=m1;
					q2<=m2;
					q3<=m3;
					q4<=m4;
					q5<=m5;

			END CASE;
	END PROCESS;
	
		
END a;