usbf_pd.vhd

USB的 这次 我这只有两个可以上载 谁能告诉我怎么办

--file usbf_pd.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity usbf_pd is
	generic
	(
		usbf_t_pid_out : std_logic_vector(3 downto 0):="0001";
		usbf_t_pid_in	:std_logic_vector(3 downto 0):="1001";
		usbf_t_pid_sof	:std_logic_vector(3 downto 0):="0101";
		usbf_t_pid_setup	:std_logic_vector(3 downto 0):="1101";
		usef_t_pid_data0	:std_logic_vector(3 downto 0):="0011";
		usef_t_pid_data1	:std_logic_vector(3 downto 0):="1011";
		usef_t_pid_data2	:std_logic_vector(3 downto 0):="0111";
		usef_t_pid_madta	:std_logic_vector(3 downto 0):="1111";
		usbf_t_pid_ack		:std_logic_vector(3 downto 0):="0010";
		usbf_t_pid_nack		:std_logic_vector(3 downto 0):="1010";
		usbf_t_pid_stall	:std_logic_vector(3 downto 0):="1110";
		usbf_t_pid_nyet		:std_logic_vector(3 downto 0):="0110";
		usbf_t_pid_pre		:std_logic_vector(3 downto 0):="1100";
		usbf_t_pid_err		:std_logic_vector(3 downto 0):="1100";
		usbf_t_pid_split	:std_logic_vector(3 downto 0):="1000";
		usbf_t_pid_ping		:std_logic_vector(3 downto 0):="0100";
		usbf_t_pid_res		:std_logic_vector(3 downto 0):="0000"
		
	);
	port
	(
		clk,rst		: in std_logic;
		rx_data		: in std_logic_vector(7 downto 0);
		rx_valid,rx_active,rx_err: in std_logic;
		--PID 数据包标
		pid_out,pid_in,pid_sof,pid_setup	:buffer std_logic;
		pid_data0,pid_data1,pid_data2,pid_mdata: buffer std_logic;
		pid_ack,pid_err,pid_split,pid_ping: buffer std_logic;
		pid_cks_err	: buffer std_logic;
		--令牌包信息输出接口
		token_fadr	: buffer std_logic_vector(6 downto 0);
		token_endp	: buffer std_logic_vector(3 downto 0);
		token_valid : buffer std_logic;
		crc5_err	: out std_logic_vector(10 downto 0);
		--
		rx_data_st	: out std_logic_vector(7 downto 0);
		rx_data_valid: out std_logic;
		rx_data_done : out std_logic;
		crc16_err	: out std_logic;
		--misc;
		seq_err : buffer std_logic
			 
	);
end entity;

architecture arch_usbf_pd of usbf_pd is
component usbf_crc5 port
	(
		crc_in : in std_logic_vector(4 downto 0);
	    din	   : in std_logic_vector(10 downto 0);
		crc_out: out std_logci_vector(4 downto 0)
	);
end component;

component usbf_crc16 port
	(
		crc_in : in std_logic_vector(15 downto 0);
	    din	   : in std_logic_vector(7 downto 0);
		crc_out: out std_logci_vector(15 downto 0)
	);
end component;
--
contant idle : std_logic_vector(3 downto 0):="0001";
contant active : std_logic_vector(3 downto 0):="0010";
contant token : std_logic_vector(3 downto 0):="0100";
contant data : std_logic_vector(3 downto 0):="1000";
signal state,next_state:std_logic_vector(3 downto 0);
signal pid:std_logic_vector(7 downto 0);
signal pid_le_sm:std_logic;
signal pid_ld_en:std_logic;
signal pid_res:std_logic;
signal pid_token:std_logic;
signal pid _data:std_logic;
signal token0,token1:std_logic_vector(7 downto 0);
signal token_le_1,token_le_2:std_logic;
signal token_crc5:std_logic_vector(4 downto 0);
signal d0,d1,d2:std_logic_vector(7 downto 0);
signal data_valid_d,:std_logic;
signal data_done:std_logic;
signal data_valid0:std_logic;
signal rxv1:std_logic;
signal rxv2:std_logic;
signal got_pid_ack:std_logic;
signal token_valid_r1:std_logic;
signal token_valid_str1;std_logic;
signal rx_active_r:std_logic;
signal crc5_out:std_logic_vector(4 downto 0);
signal crc5_out2:std_logic_vector(4 downto 0);
signal crc16_clr:std_logic;
signal crc16_sum:std_logic_vector(7 downto 0);
signal crc16_out:std_logic_vector(10 downto 0);
begin
pid_ld_en<=pid_le_sm and rx_active and rx_valid;
process(clk,rst)
begin
	if rst='0' then
		pid<="11110000";
	elsif clk'event and clk='1' then
		if pid_ld_en='1' then
			pid<=rx_data;
		end if;
	end if
end process;
process(pid)
begin
	if pid(3 downto 0)/=not(pid(7 downto 4)) then
		pid_cks_err<='1';
	else
		pid_cks_err<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_in then
		pid_in<='1';
	else 
		pid_in<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_sof then
	    pid_sof<='1';
	else
		pid_sof<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_setup then
	    pid_setup<='1';
	else
		pid_setup<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_data0 then
	    pid_data0<='1';
	else
		pid_data0<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_data1 then
	    pid_data1<='1';
	else
		pid_data1<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_data2 then
	    pid_data2<='1';
	else
		pid_data2<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_mdata then
	    pid_mdata<='1';
	else
		pid_mdata<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_ack then
	    pid_ack<='1';
	else
		pid_ack<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_nack then
	    pid_nack<='1';
	else
		pid_nack<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_stall then
	    pid_stall<='1';
	else
		pid_stall<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_nyet then
	    pid_nyet<='1';
	else
		pid_nyet<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_pre then
	    pid_pre<='1';
	else
		pid_pre<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_err then
	    pid_err<='1';
	else
		pid_err<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_split then
	    pid_split<='1';
	else
		pid_split<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_ping then
	    pid_ping<='1';
	else
		pid_ping<='0';
	end if;
	if pid(3 downto 0)=usbf_t_pid_res then
	    pid_res<='1';
	else
		pid_res<='0';
	end if;
end process;
pid_token<=pid_out or pid_in or pid_sof or pid_setup or pid_ping;
pid_data<=pid_data0 or pid_data1 or pid_data2 or pid_mdata;
process(clk)
begin
	if clk'event and clk='1' then
		if token_le_1='1' then
			token0<=rx_data;
		end if;
	end if;
end process;
process(clk)
begin
 if clk'event and clk='1' then
	if token_le_2='1' then
		token1<=rx_data;
	end if;
end if;
end process;

process(clk)
begin
 if clk'event and clk='1' then
	token_valid_r1<=token_le_2;
 end if;
end process;

process(clk)
begin
	if clk'event and clk='1' then
		token_valid_str1<=token_valid_r1 or got_pid_ack;
	end if;
end process;
token_valid<=token_valid_str1;