rs232_t.vhd

FPGA的串口通信程序

--the rs232 send module
--include one clk and one send component

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity rs232_t is										--send and pll1的物理连接
port 
(
	  clk  		: in  std_logic ;
   	  ctrl		: in  std_logic;
	  datain	: in  std_logic_vector (7 downto 0);
	  txd    	: out std_logic
) ;
end rs232_t ;

architecture rtl of rs232_t is

signal clkin : std_logic ;
signal dataout : std_logic_vector(7 downto 0);

component pll1
PORT
(
	inclk0		: IN STD_LOGIC  := '0';
	c0			: OUT STD_LOGIC 
);
END component;

component send
port 
(
	  clk16x : in std_logic;
	  clk	 : in std_logic;
	  ctrl	 : in std_logic;
	  datain : in std_logic_vector(7 downto 0) ;
	  dout	 : out std_logic
);
end component;

begin

process(clk)
begin
if clk'event and clk = '1' then
dataout(0) <= datain(7);
dataout(1) <= datain(6);
dataout(2) <= datain(5);
dataout(3) <= datain(4);
dataout(4) <= datain(3);
dataout(5) <= datain(2);
dataout(6) <= datain(1);
dataout(7) <= datain(0);
end if;
end process;						--rs232发送、接收和hdl描述数据的高低位转换
									--接收时得到的数据在image1模块里面处理
u1 : pll1 port map (clk, clkin);
u2 : send port map (clkin,clk,ctrl,dataout,txd);

end;