pll1.vhd

来自「FPGA的串口通信程序」· VHDL 代码 · 共 35 行

--generate the clk to collect the signal from rs232
--generate the clk 'clk16x'

--the clk also can be used to send data from rs232

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity pll1 is
port (inclk0 : in std_logic ;	--原始时钟频率40MHz
	  c0 : out std_logic		--rs232采集所需频率clk16x,rs232传送比特位宽的'16倍'
) ;
end pll1 ;

architecture counter of pll1 is

signal number : unsigned (8 downto 0) ;
begin

process(inclk0)
begin

if inclk0'event and inclk0 = '1' then
if std_logic_vector(number) = "100000011"  then		--计数器实现时钟的转换
number <= "000000000";
c0 <= '1';
else number <= number + "000000001";
c0 <= '0';
end if;
end if;
end process;

end;