ymdhms.vhd

电子打铃器 在max plus 2 下编译通过

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ymdhms is
port(
	
	setn:std_logic_vector(5 downto 0);
	ena,clk:in std_logic;
	cosecond: out std_logic;	
	year1,year2,month1,month2,day1,day2,hour1,hour2,minute1,minute2,second1,second2: out std_logic_vector(3 downto 0));
end ymdhms;

architecture rtl of ymdhms is
component cnt60
port(
	
	clk: in std_logic;
	ena: in std_logic;	
	co: out std_logic;
	data1,data2: out std_logic_vector(3 downto 0));
end component;

component cnt24
port(
	
	clk: in std_logic;
	ena: in std_logic;	
	co: out std_logic;
	data1,data2: out std_logic_vector(3 downto 0));
end component;

component cnt31
port(
	
	clk: in std_logic;
	ena: in std_logic;	
	co: out std_logic;
	data1,data2: out std_logic_vector(3 downto 0));
end component;

component cnt12
port(
	
	clk: in std_logic;
	ena: in std_logic;	
	co: out std_logic;
	data1,data2: out std_logic_vector(3 downto 0));
end component;

component cnt100
port(
	
	clk: in std_logic;
	ena: in std_logic;	
	co: out std_logic;
	data1,data2: out std_logic_vector(3 downto 0));
end component;

signal cosec,comin,cohou,coday,comonth,coyear,en,tempcosec,tempcomin,tempcohou,tempcoday,tempcomonth:std_logic;
--signal ensec,enmin,enhou,enday,enmon,enyea:std_logic_vector(1 downto 0);

begin
	en<=ena or setn(0);
	tempcosec<=setn(1) or cosec;
	tempcomin<=setn(2) or comin;
	tempcohou<=setn(3) or cohou;
	tempcoday<=setn(4) or coday;
	tempcomonth<=setn(5) or comonth;
	u1:cnt60
	port map(clk,en,cosec,second1,second2);
	u2:cnt60
	port map(clk,tempcosec,comin,minute1,minute2);
	u3:cnt24
	port map(clk,tempcomin,cohou,hour1,hour2);
	u4:cnt31
	port map(clk,tempcohou,coday,day1,day2);
	u5:cnt12
	port map(clk,tempcoday,comonth,month1,month2);
	u6:cnt100
	port map(clk,tempcomonth,coyear,year1,year2);
	cosecond<=cosec;
end rtl;