pcore.vhd

基于SDRAM总线的加速部件核心和相关论文说明

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.all;
--synopsys translate_on

entity pcore is
port (
	clk: in std_logic;
	clkdiv: in std_logic;
	rst: in std_logic;
	read: in std_logic;
	write: in std_logic;
	addr: in std_logic_vector(13 downto 0);
	din: in std_logic_vector(63 downto 0);
	dout: out std_logic_vector(63 downto 0);
	dmask: in std_logic_vector(63 downto 0);
	extin: in std_logic_vector(25 downto 0);
	extout: out std_logic_vector(25 downto 0);
	extctrl: out std_logic_vector(25 downto 0) );
end pcore;

architecture syn of pcore is

	component RAMB4_S16 is
	port (
		WE: in std_logic;
		EN: in std_logic;
		RST: in std_logic;
		CLK: in std_logic;
		ADDR: in std_logic_vector(7 downto 0);
		DI: in std_logic_vector(15 downto 0);
		DO: out std_logic_vector(15 downto 0) );
	end component RAMB4_S16;

	component RAMB4_S16_S16 is
	port (
		WEA: in std_logic;
		ENA: in std_logic;
		RSTA: in std_logic;
		CLKA: in std_logic;
		ADDRA: in std_logic_vector(7 downto 0);
		DIA: in std_logic_vector(15 downto 0);
		DOA: out std_logic_vector(15 downto 0);
		WEB: in std_logic;
		ENB: in std_logic;
		RSTB: in std_logic;
		CLKB: in std_logic;
		ADDRB: in std_logic_vector(7 downto 0);
		DIB: in std_logic_vector(15 downto 0);
		DOB: out std_logic_vector(15 downto 0) );
	end component;

	signal VDD: std_logic;
	signal GND: std_logic;

	signal cnt_en: std_logic;
	signal addr_cnt: std_logic_vector(7 downto 0);
	signal dia: std_logic_vector(15 downto 0);

	type state_type is (INI, ST1, ST2);
	signal state: state_type;
	signal st: std_logic_vector(1 downto 0);

begin

	VDD <= '1';
	GND <= '0';

	-- single port BlockRAM with 16-bit databus and 8-bit address
	-- the address is connected to the lower 8 bits of the systerm memory
	-- address, the data lines are connected to the lower 16 bits of the
	-- system memory data bus
	U_RAM1: RAMB4_S16 port map (
		WE => write,
		EN => VDD,
		RST => rst,
		CLK => clk,
		ADDR => addr(7 downto 0),
		DI => din(15 downto 0),
		DO => dout(15 downto 0) );

	-- counter enable control, if state is ST2 then counter start, else
	-- counter stop
	cnt_en <= '1' when state = ST2 else '0';
	-- 8-bit counter controlled by state and clock by clkdiv, half of the
	-- system clock rate
	CNT: process(clkdiv, rst)
	begin
		if rst = '1' then
			addr_cnt <= (others => '0');
		elsif clkdiv'event and clkdiv = '1' then
			if cnt_en = '1' then
				addr_cnt <= addr_cnt + 1;
			end if;
		end if;
	end process CNT;

	-- dual port BlockRAM with 16-bit databus and 8-bit address
	-- one port is written by the counter and the other is read by host
	-- the address counter initialize the contents and then the host read
	-- them
	dia <= addr_cnt&"01011010";
	U_RAM2: RAMB4_S16_S16 port map (
		WEA => cnt_en,
		ENA => VDD,
		RSTA => rst,
		CLKA => clkdiv,
		ADDRA => addr_cnt,
		DIA => dia,
		DOA => open,
		WEB => GND,
		ENB => VDD,
		RSTB => rst,
		CLKB => clk,
		ADDRB => addr(7 downto 0),
		DIB => dia,
		DOB => dout(31 downto 16) );

	-- Finte State Machine with 3 states
	-- when system start up, stat is INI
	-- after that, the state will advance to ST1
	-- if a write in address 0xFF (*8 in software), the state altered
	FSM: process(clk, rst)
	begin
		if rst = '1' then
				state <= INI;
		elsif clk'event and clk = '1' then
			case state is
			when INI =>
				state <= ST1;
			when ST1 =>
				if write = '1' and addr(7 downto 0) = "11111111" then
					state <= ST2;
				else
					state <= ST1;
				end if;
			when ST2 =>
				if write = '1' and addr(7 downto 0) = "11111111" then
					state <= ST1;
				else
					state <= ST2;
				end if;
			when others =>
				state <= INI;
			end case;
		end if;
	end process FSM;

	-- output the state to databus
	st <= "00" when state = INI else
		"01" when state = ST1 else
		"10";
	dout(33 downto 32) <= st;
	dout(63 downto 34) <= din(63 downto 34);

	-- output debug signals to external header
	extout(0) <= clkdiv;
	extout(1) <= rst;
	extout(2) <= read;
	extout(3) <= write;
	extout(5 downto 4) <= st;
	extout(13 downto 6) <= addr(7 downto 0);
	extout(14) <= cnt_en;
	extout(22 downto 15) <= addr_cnt;
	extout(25 downto 23) <= (others => GND);
	-- enable external header for output
	extctrl <= (others => GND);

end syn;