代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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vhd test_regdmtxdrv.vhd

-------------------------------------------------------------------------------- -- Test module for regDMtxDrv -- T.Kohno -- Rev. 0.1.1 / 9, Jun., 2005 --------------------------------------------
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vhd regi2cmaster.vhd

-------------------------------------------------------------------------------- -- regI2cMaster (i2c Master Unit /w register I/F) -- Takashi Kohno (DigiCat) -- Rev. 0.5.0c / 16, Jun., 2005 -- -
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vhd regi2cslave.vhd

-------------------------------------------------------------------------------- -- regI2cSlave (i2c Slave Unit /w register I/F) -- Takashi Kohno (DigiCat) -- Rev. 0.5.0c / 16, Jun., 2005 -- ---
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vhd clock_pkg.vhd

library ieee; use ieee.std_logic_1164.all;component cnt60 is port(ch,cl : buffer std_logic_vector (3 downto 0); clk : in std_logic ; carry: buffer std_logic ); end component use
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vhd system.vhd

library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity system is port(reset:in std_logic; on_off:in std_logic; cl
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txt system.txt

library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity system is port(reset:in std_logic; on_off:in std_logic; cl
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vhd dff8.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff8 IS PORT( clk : IN STD_LOGIC; clear : IN STD_LOGIC; Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR
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vhdl yiwei.vhdl

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for ins
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vhf mimasuo.vhf

-- VHDL model created from mimasuo.sch - Thu Apr 19 19:18:50 2007 library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vc
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vhd clk_divide_3.vhd

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY clk_divide_3 IS PORT ( clkin ,rst: IN STD_LOGIC; clkout : OUT STD_LOGIC; t1,t2: out std_logic ); END clk_divide_3;
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