regi2cslave.vhd

DesignWave 2005 8 Verilog Example

--------------------------------------------------------------------------------
-- regI2cSlave (i2c Slave Unit /w register I/F)
-- Takashi Kohno (DigiCat)
-- Rev. 0.5.0c  / 16, Jun., 2005
--
----------------------------------------
--
-- Copyright (c)   2005   Takashi Kohno
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or any later version.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
--------------------------------------------------------------------------------
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;


entity regI2cSlave is
	generic( CKEDIVWIDTH		: integer := 4 ;
			 CKEDIV				: integer := 10
			 ) ;
	port(	CLK, nRST			: in std_logic ;
			
			-- Register I/F
			WrEn, RdEn			: in std_logic ;  -- Write Enable / Read Enable
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;  -- Address in the Unit
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;
			Int					: out std_logic ;  -- Interruption output (level drive)

			-- i2c bus
			SCL, SDA			: in std_logic ;
			slvSCL, slvSDA		: out std_logic
			) ;
end regI2cSlave ;



architecture RTL of regI2cSlave is

component rif_i2cSlave
	port(	CLK, nRST			: in std_logic ;
			CKE					: in std_logic ;  -- CLK enable for sampling clock
			
			-- Register I/F
			WrEn, RdEn			: in std_logic ;
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;
			Int					: out std_logic ;

			-- Local bus for slave functions
			syncRST				: out std_logic ;
			-- Transaction query
			SReq				: in std_logic ;
			Si2cAdrs			: in std_logic_vector(6 downto 0) ;
			SRnW				: in std_logic ;
			SAck				: out std_logic ;

			-- Slave write stream
			SwrDReq				: in std_logic ;
			SwrData				: in std_logic_vector(7 downto 0) ;
			SwrTerm				: out std_logic ;
			SwrDRdy				: out std_logic ;
			
			-- Slave read stream
			SrdDReq				: in std_logic ;
			SrdData				: out std_logic_vector(7 downto 0) ;
			SrdDRdy				: out std_logic ;

			-- Status Reports
			srpTerm				: in std_logic ;
			srpAbort			: in std_logic ;
			srpBFree			: in std_logic ;
			srpBObsc			: in std_logic ;

			-- Timing Parameters
			Dsup				: out std_logic_vector(1 downto 0)
			) ;
end component ;

component i2cSlave
	port(	CLK, nRST, syncRST	: in std_logic ;
			CKE					: in std_logic ;  -- CLK enable for sampling clock
			
			-- i2c bus
			SCL, SDA			: in std_logic ;
			slvSCL, slvSDA		: out std_logic ;

			-- Local bus for slave functions
			-- Transaction detection
			SReq				: out std_logic ;
			Si2cAdrs			: out std_logic_vector(6 downto 0) ;
			SRnW				: out std_logic ;
			SAck				: in std_logic ;

			-- Slave write stream
			SwrDReq				: out std_logic ;
			SwrData				: out std_logic_vector(7 downto 0) ;
			SwrTerm				: in std_logic ;
			SwrDRdy				: in std_logic ;

			--Slave read stream
			SrdDReq				: out std_logic ;
			SrdData				: in std_logic_vector(7 downto 0) ;
			SrdDRdy				: in std_logic ;

			-- Status Reports
			srpTerm				: out std_logic ;
			srpAbort			: out std_logic ;
			srpBFree			: out std_logic ;
			srpBObsc			: out std_logic ;

			-- Parameters
			Dsup			: in std_logic_vector(1 downto 0)
			) ;
end component ;


-- connection signals
signal CKE				: std_logic ;  -- CLK enable for sampling clock
signal syncRST			: std_logic ;

signal SReq				: std_logic ;
signal Si2cAdrs			: std_logic_vector(6 downto 0) ;
signal SRnW				: std_logic ;
signal SAck				: std_logic ;
signal SwrDReq			: std_logic ;
signal SwrData			: std_logic_vector(7 downto 0) ;
signal SwrTerm			: std_logic ;
signal SwrDRdy			: std_logic ;
signal SrdDReq			: std_logic ;
signal SrdData			: std_logic_vector(7 downto 0) ;
signal SrdDRdy			: std_logic ;
signal srpTerm			: std_logic ;
signal srpAbort			: std_logic ;
signal srpBFree			: std_logic ;
signal srpBObsc			: std_logic ;
signal Dsup				: std_logic_vector(1 downto 0) ;

-- CKE generator
signal CKECount			: std_logic_vector(CKEDIVWIDTH - 1 downto 0) ;


begin

-- component instantiation
	rifUNIT: rif_i2cSlave
		port map (	CLK => CLK, nRST => nRST,
					CKE => CKE,
					WrEn => WrEn, RdEn => RdEn,
					Usel => Usel,
					Uadrs => Uadrs,
					Din => Din,
					Dout => Dout,
					Int => Int,
					syncRST => syncRST,
					SReq => SReq,
					Si2cAdrs => Si2cAdrs,
					SRnW => SRnW,
					SAck => SAck,
					SwrDReq => SwrDReq,
					SwrData => SwrData,
					SwrTerm => SwrTerm,
					SwrDRdy => SwrDRdy,
					SrdDReq => SrdDReq,
					SrdData => SrdData,
					SrdDRdy => SrdDRdy,
					srpTerm => srpTerm,
					srpAbort => srpAbort,
					srpBFree => srpBFree,
					srpBObsc => srpBObsc,
					Dsup => Dsup
					) ;

	i2cSlaveUNIT: i2cSlave
		port map (	CLK => CLK, nRST => nRST, syncRST => syncRST,
					CKE => CKE,
					SCL => SCL, SDA => SDA,
					slvSCL => slvSCL, slvSDA => slvSDA,
					SReq => SReq,
					Si2cAdrs => Si2cAdrs,
					SRnW => SRnW,
					SAck => SAck,
					SwrDReq	=> SwrDReq,
					SwrData => SwrData,
					SwrTerm => SwrTerm,
					SwrDRdy => SwrDRdy,
					SrdDReq => SrdDReq,
					SrdData => SrdData,
					SrdDRdy => SrdDRdy,
					srpTerm => srpTerm,
					srpAbort => srpAbort,
					srpBFree => srpBFree,
					srpBObsc => srpBObsc,
					Dsup => Dsup
					) ;



-- Clock Enable  Generation
	CKEGEN: process(CLK, nRST)
	begin
		if nRST = '0' then
			CKECount <= (others => '1') ;
		elsif rising_edge(CLK) then
			if CKE = '1' then
				CKECount <= CONV_STD_LOGIC_VECTOR(CKEDIV, CKEDIVWIDTH) ;
			else
				CKECount <= unsigned(CKECount) - 1 ;
			end if ;
		end if ;
	end process ;

	CKE <= '1' when CKECount = CONV_STD_LOGIC_VECTOR(0, CKEDIVWIDTH) else
		   '0' ;


end RTL ;