mimasuo.vhf

8位密码锁的实现

-- VHDL model created from mimasuo.sch - Thu Apr 19 19:18:50 2007


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity mimasuo is
   port ( CLK   : in    std_logic; 
          COL   : in    std_logic_vector (3 downto 0); 
          EQUAL : out   std_logic; 
          neq   : out   std_logic; 
          Q     : out   std_logic_vector (6 downto 0); 
          ROW   : out   std_logic_vector (3 downto 0); 
          WX    : out   std_logic_vector (7 downto 0));
end mimasuo;

architecture BEHAVIORAL of mimasuo is
   signal XLXN_3   : std_logic;
   signal XLXN_6   : std_logic_vector (2 downto 0);
   signal XLXN_7   : std_logic_vector (3 downto 0);
   signal XLXN_8   : std_logic_vector (3 downto 0);
   signal XLXN_9   : std_logic_vector (3 downto 0);
   signal XLXN_10  : std_logic_vector (3 downto 0);
   signal XLXN_11  : std_logic_vector (3 downto 0);
   signal XLXN_12  : std_logic_vector (3 downto 0);
   signal XLXN_13  : std_logic_vector (3 downto 0);
   signal XLXN_14  : std_logic_vector (3 downto 0);
   signal XLXN_17  : std_logic;
   signal XLXN_18  : std_logic;
   signal XLXN_22  : std_logic_vector (3 downto 0);
   signal XLXN_107 : std_logic;
   signal XLXN_113 : std_logic;
   signal XLXN_114 : std_logic_vector (3 downto 0);
   signal XLXN_115 : std_logic;
   component fpq10ms
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component keyval
      port ( clkscan : in    std_logic; 
             keyin   : in    std_logic_vector (3 downto 0); 
             pressed : out   std_logic; 
             comp    : out   std_logic; 
             rstcode : out   std_logic; 
             clr_out : out   std_logic; 
             keydrv  : out   std_logic_vector (3 downto 0); 
             value   : out   std_logic_vector (3 downto 0));
   end component;
   
   component se8
      port ( CP : in    std_logic; 
             s  : out   std_logic_vector (2 downto 0));
   end component;
   
   component xzq81
      port ( S  : in    std_logic_vector (2 downto 0); 
             Q  : out   std_logic_vector (3 downto 0); 
             Q1 : in    std_logic_vector (3 downto 0); 
             Q2 : in    std_logic_vector (3 downto 0); 
             Q3 : in    std_logic_vector (3 downto 0); 
             Q4 : in    std_logic_vector (3 downto 0); 
             Q5 : in    std_logic_vector (3 downto 0); 
             Q6 : in    std_logic_vector (3 downto 0); 
             Q7 : in    std_logic_vector (3 downto 0); 
             Q8 : in    std_logic_vector (3 downto 0); 
             WX : out   std_logic_vector (7 downto 0));
   end component;
   
   component yiwei
      port ( EN      : in    std_logic; 
             clk     : in    std_logic; 
             clr     : in    std_logic; 
             rstcode : in    std_logic; 
             comp    : in    std_logic; 
             d       : in    std_logic_vector (3 downto 0); 
             s       : out   std_logic; 
             q       : out   std_logic; 
             K1      : out   std_logic_vector (3 downto 0); 
             K2      : out   std_logic_vector (3 downto 0); 
             K3      : out   std_logic_vector (3 downto 0); 
             K4      : out   std_logic_vector (3 downto 0); 
             K5      : out   std_logic_vector (3 downto 0); 
             K6      : out   std_logic_vector (3 downto 0); 
             K7      : out   std_logic_vector (3 downto 0); 
             K8      : out   std_logic_vector (3 downto 0));
   end component;
   
   component fpq01ms
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component ymq
      port ( A : in    std_logic_vector (3 downto 0); 
             Q : out   std_logic_vector (6 downto 0));
   end component;
   
begin
   XLXI_1 : fpq10ms
      port map (CLK=>CLK, CP=>XLXN_113);
   
   XLXI_2 : keyval
      port map (clkscan=>XLXN_113, keyin(3 downto 0)=>COL(3 downto 0),
            clr_out=>XLXN_18, comp=>XLXN_107, keydrv(3 downto 0)=>ROW(3 downto
            0), pressed=>XLXN_17, rstcode=>XLXN_115, value(3 downto
            0)=>XLXN_114(3 downto 0));
   
   XLXI_3 : se8
      port map (CP=>XLXN_3, s(2 downto 0)=>XLXN_6(2 downto 0));
   
   XLXI_4 : xzq81
      port map (Q1(3 downto 0)=>XLXN_7(3 downto 0), Q2(3 downto 0)=>XLXN_8(3
            downto 0), Q3(3 downto 0)=>XLXN_9(3 downto 0), Q4(3 downto
            0)=>XLXN_10(3 downto 0), Q5(3 downto 0)=>XLXN_11(3 downto 0), Q6(3
            downto 0)=>XLXN_12(3 downto 0), Q7(3 downto 0)=>XLXN_13(3 downto
            0), Q8(3 downto 0)=>XLXN_14(3 downto 0), S(2 downto 0)=>XLXN_6(2
            downto 0), Q(3 downto 0)=>XLXN_22(3 downto 0), WX(7 downto 0)=>WX(7
            downto 0));
   
   XLXI_5 : yiwei
      port map (clk=>XLXN_113, clr=>XLXN_18, comp=>XLXN_107, d(3 downto
            0)=>XLXN_114(3 downto 0), EN=>XLXN_17, rstcode=>XLXN_115, K1(3
            downto 0)=>XLXN_7(3 downto 0), K2(3 downto 0)=>XLXN_8(3 downto 0),
            K3(3 downto 0)=>XLXN_9(3 downto 0), K4(3 downto 0)=>XLXN_10(3
            downto 0), K5(3 downto 0)=>XLXN_11(3 downto 0), K6(3 downto
            0)=>XLXN_12(3 downto 0), K7(3 downto 0)=>XLXN_13(3 downto 0), K8(3
            downto 0)=>XLXN_14(3 downto 0), q=>EQUAL, s=>neq);
   
   XLXI_6 : fpq01ms
      port map (CLK=>CLK, CP=>XLXN_3);
   
   XLXI_7 : ymq
      port map (A(3 downto 0)=>XLXN_22(3 downto 0), Q(6 downto 0)=>Q(6 downto
            0));
   
end BEHAVIORAL;