test_regdmtxdrv.vhd

DesignWave 2005 8 Verilog Example

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-- Test module for regDMtxDrv
-- T.Kohno
-- Rev. 0.1.1 / 9, Jun., 2005
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library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;

--library lpm ;
--use lpm.lpm_components.all ;

entity test_regDMtxDrv is
	port(	CLK, nRST			: in std_logic ;

			-- Test board I/F
			rawSWin				: in std_logic_vector(2 downto 0) ;
			TailMonitor			: out std_logic ;
			WrapMonitor			: out std_logic ;
			MonitorEnable		: out std_logic ;

			-- Matrix Drivers
			drvRow0				: out std_logic_vector(7 downto 0) ;
			drvRow1				: out std_logic_vector(7 downto 0) ;
			drvCol				: out std_logic_vector(23 downto 0)
			) ;
end test_regDMtxDrv ;

architecture RTL of test_regDMtxDrv is

component regDMtxDrv
	generic ( COLSIZE			: integer := 3 ;
			  VBDIV				: integer := 1 ;
			  RAMWAIT			: integer := 1  -- 0 to 7
			  ) ;
	port(	CLK, nRST			: in std_logic ;

			-- Register I/F
			WrEn, RdEn			: in std_logic ;
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;

			-- Ram I/F
			RamAdrs				: out std_logic_vector(5 + VBDIV downto 0) ;
			RamRdEn				: out std_logic ;
			RamData				: in std_logic_vector(64 / (2 ** VBDIV) - 1 downto 0) ;

			-- Matrix Drivers
			drvRow0				: out std_logic_vector(7 downto 0) ;
			drvRow1				: out std_logic_vector(7 downto 0) ;
			drvCol				: out std_logic_vector(COLSIZE * 8 - 1 downto 0)
			) ;
end component ;

constant COLSIZE : integer := 3 ;
constant VBDIV : integer := 1 ;

signal WrEn, RdEn		: std_logic ;
signal Usel				: std_logic ;  -- Unit select
signal Uadrs			: std_logic_vector(2 downto 0) ;
signal Din				: std_logic_vector(7 downto 0) ;
signal Dout				: std_logic_vector(7 downto 0) ;

signal RamAdrs		: std_logic_vector(5 + VBDIV downto 0) ;
signal RamRdEn		: std_logic ;
signal RamData		: std_logic_vector(64 / (2 ** VBDIV) - 1 downto 0) ;

--signal drvRow0		: std_logic_vector(7 downto 0) ;
--signal drvRow1		: std_logic_vector(7 downto 0) ;
--signal drvCol		: std_logic_vector(COLSIZE * 8 - 1 downto 0) ;


-- for stims.
signal SimCode					: integer ;
type StimState is (RST, SETUP, STIM) ;
signal StimQ		: StimState ;

signal VRHead, VRTail	: std_logic_vector(5 downto 0) ;
signal regAdrs			: std_logic_vector(2 downto 0) ;
signal VRTailMode		: std_logic ;
signal WrapMode			: std_logic ;

-- Switch input processors
signal CLKCntr			: std_logic_vector(11 downto 0);
signal SWin				: std_logic_vector(2 downto 0) ;
signal dSWin1, dSWin2	: std_logic_vector(2 downto 0) ;
signal dSWin, efSWin	: std_logic_vector(2 downto 0) ;


begin

-- component instantiation
	DUT: regDMtxDrv
		generic  map ( COLSIZE => COLSIZE,
					   VBDIV => VBDIV,
					   RAMWAIT => 2
					   )
		port map(	CLK => CLK, nRST => nRST,
					WrEn => WrEn, RdEn => RdEn,
					Usel =>	Usel,
					Uadrs => Uadrs,
					Din => Din,
					Dout => Dout,
					RamAdrs => RamAdrs,
					RamRdEn => RamRdEn,
					RamData => RamData,
					drvRow0 => drvRow0,
					drvRow1 => drvRow1,
					drvCol => drvCol
					) ;

	MonitorEnable <= '0' ;


-- stimuli
	RamDataGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			RamData <= (others => '0') ;
		elsif rising_edge(CLK) then
			if RamAdrs(2) = '0' then  	-- not blank
				case RamAdrs(4 downto 3) is
					when "00" =>
						for i in 0 to 3 loop
							RamData(i * 8 + 1 downto i * 8) <= CONV_STD_LOGIC_VECTOR(i, 2) ;
							RamData(i * 8 + 3 downto i * 8 + 2) <= RamAdrs(1 downto 0) ;
							RamData(i * 8 + 5 downto i * 8 + 4) <= CONV_STD_LOGIC_VECTOR(i, 2) ;
							RamData(i * 8 + 7 downto i * 8 + 6) <= RamAdrs(1 downto 0) ;
						end loop ;
					when "01" =>
						for i in 0 to 3 loop
							RamData(i * 8 + 1 downto i * 8) <= (others => '0') ;
							RamData(i * 8 + 3 downto i * 8 + 2) <= (others => '0') ;
							RamData(i * 8 + 5 downto i * 8 + 4) <= CONV_STD_LOGIC_VECTOR(i, 2) ;
							RamData(i * 8 + 7 downto i * 8 + 6) <= RamAdrs(1 downto 0) ;
						end loop ;
					when "10" =>
						for i in 0 to 3 loop
							RamData(i * 8 + 1 downto i * 8) <= CONV_STD_LOGIC_VECTOR(i, 2) ;
							RamData(i * 8 + 3 downto i * 8 + 2) <= RamAdrs(1 downto 0) ;
							RamData(i * 8 + 5 downto i * 8 + 4) <= (others => '0') ;
							RamData(i * 8 + 7 downto i * 8 + 6) <= (others => '0') ;
						end loop ;
					when "11" =>
						for i in 0 to 3 loop
							RamData(i * 8 + 1 downto i * 8) <= "11" ;
							RamData(i * 8 + 3 downto i * 8 + 2) <= "01" ;
							RamData(i * 8 + 5 downto i * 8 + 4) <= "11" ;
							RamData(i * 8 + 7 downto i * 8 + 6) <= "01" ;
						end loop ;
					when others =>
				end case ;
			else
				for i in 0 to 1 loop
					RamData(i * 16 + 3 downto i * 16) <= (others => RamAdrs(5)) ;
					RamData(i * 16 + 7 downto i * 16 + 4) <= (others => RamAdrs(5)) ;
					RamData(i * 16 + 11 downto i * 16 + 8) <= "0000" ;
					RamData(i * 16 + 15 downto i * 16 + 12) <= "0000" ;
				end loop ;
			end if ;
		end if ;
	end process ;


	TestController: process(CLK, nRST)
	begin
		if nRST = '0' then
			StimQ <= RST ;
			regAdrs <= (others => '0') ;
			VRHead <= (others => '0') ;
			VRTail <= (others => '1') ;
		elsif rising_edge(CLK) then
			case StimQ is
				when RST =>
					StimQ <= SETUP ;
					regAdrs <= (others => '0') ;
					VRHead <= (others => '0') ;
					VRTail <= (others => '1') ;
					WrEn <= '0' ;
				when SETUP =>
					regAdrs <= unsigned(regAdrs) + 1 ;
					Uadrs <= regAdrs ;
					WrEn <= '1' ;
					case regAdrs is
						when "000" =>
							Din <= "00000000" ;
						when "001" =>
							Din <= "00000011" ;
						when "010" =>
							Din <= "00000000" ;
						when "011" =>
							Din <= "00000001" ;
						when "100" =>
							Din <= "00000001" ;
						when "101" =>
							Din <= ("00" & VRHead) ;
						when "110" =>
							if VRTailMode = '1' then
								Din <= ("00" & VRTail) ;
							else
								Din <= "11111111" ;
							end if ;
						when "111" =>
							Din <= ('1' & WrapMode & "000000") ;
							StimQ <= STIM ;
						when others =>
					end case ;
				when STIM =>
					WrEn <= '0' ;
					if efSWin(0) = '1' then
						regAdrs <= (others => '0') ;
						VRHead <= unsigned(VRHead) + 1 ;
						VRTail <= unsigned(VRTail) + 1 ;
						StimQ <= SETUP ;
					end if ;
				when others =>
					StimQ <= RST ;
			end case ;
		end if ;
	end process ;

	Usel <= '1' ;
	RdEn <= '0' ;
					
	VRTailModeHolder: process(CLK, nRST)
	begin
		if nRST = '0' then
			VRTailMode <= '0' ;
		elsif rising_edge(CLK) then
			if efSWin(1) = '1' then
				VRTailMode <= not VRTailMode ;
			end if ;
		end if ;
	end process ;

	TailMonitor <= not VRTailMode ;
			
	WrapModeHolder: process(CLK, nRST)
	begin
		if nRST = '0' then
			WrapMode <= '0' ;
		elsif rising_edge(CLK) then
			if efSWin(2) = '1' then
				WrapMode <= not WrapMode ;
			end if ;
		end if ;
	end process ;

	WrapMonitor <= not WrapMode ;



	-- Switch input detectors
	SWfilt: process(CLK, nRST)
	begin
		if nRST = '0' then
			CLKCntr <= (others => '0') ;
			dSWin1 <= (others => '0') ;
			dSWin2 <= (others => '0') ;
		elsif rising_edge(CLK) then
			CLKCntr <= unsigned(CLKCntr) + 1 ;
			if CLKCntr = "000000000000" then
				dSWin1 <= rawSWin ;
				dSWin2 <= dSWin1 ;
				for i in 0 to 2 loop
					if dSWin1(i) = dSWin2(i) then
						SWin(i) <= dSWin2(i) ;
					end if ;
				end loop ;
			end if ;
		end if ;
	end process ;

	SWdetect: process(CLK, nRST)
	begin
		if nRST = '0' then
			dSWin <= (others => '0') ;
		elsif rising_edge(CLK) then
			dSWin <= SWin ;
		end if ;
	end process ;

	DWDif: for i in 0 to 2 generate
		efSWin(i) <= '1' when dSWin(i) = '0' and SWin(i) = '1' else
					 '0' ;
	end generate ;
	



end RTL ;