clock_pkg.vhd

基于VHDL的电子钟 实现一个简单的电子钟

library ieee;
use ieee.std_logic_1164.all;component cnt60 is
	port(ch,cl : buffer std_logic_vector (3 downto 0);
      	 clk : in std_logic ;
		 carry: buffer std_logic
	); 
	end component 
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package clock_pkg is
	component hour is
	port( 	hh,hl : buffer std_logic_vector (3 downto 0);
      	    clk : in std_logic;
	        carry: buffer std_logic   
	);
	 end component ;
	
	;
	
	component day is
	port(dh,dl: buffer std_logic_vector (3 downto 0);
      	clk : in std_logic;
	     carry2: in std_logic_vector (1 downto 0);
	     carry1: buffer std_logic     
	); 
	end component ;
	
	component month is
	port(mh,ml : buffer std_logic_vector (3 downto 0);
      	clk : in std_logic;
	    carry1: buffer std_logic;   
        carry2: buffer std_logic_vector (1 downto 0)   
	); 
	end component ;
	
	component year is
	port(yh,yl : buffer std_logic_vector (3 downto 0);
      	clk : in std_logic
	); 
	end component ;
end package ;