system.txt

我的课程设计

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

 entity system is
   port(reset:in std_logic;
        on_off:in std_logic;
        clk:in std_logic;
        number10:in std_logic_vector(3 downto 0);
        number01:in std_logic_vector(3 downto 0); 

       out10:out std_logic_vector(6 downto 0);
       out01:out std_logic_vector(6 downto 0);
        speaker:out std_logic);
  end system;



 architecture behave of system is

  signal time10:std_logic_vector(3 downto 0);
  signal time01:std_logic_vector(3 downto 0);
  


component set
      port(reset:in std_logic;
      number10:in std_logic_vector(3 downto 0);
      number01:in std_logic_vector(3 downto 0);
      time10:out std_logic_vector(3 downto 0);
      time01:out std_logic_vector(3 downto 0));
end component;

component count
   port(clk:in std_logic;
       reset:in std_logic;
       on_off:in std_logic;
       time10:in std_logic_vector(3 downto 0);
       time01:in std_logic_vector(3 downto 0);
       
       out10:out std_logic_vector(6 downto 0);
       out01:out std_logic_vector(6 downto 0);
       speaker:out std_logic);
end component;


begin
   u0:set
     port map(reset,number10,number01,time10,time01);
   u1:count
     port map(clk,reset,on_off,time10,time01,out10,out01,speaker);
   
end behave;