regi2cmaster.vhd

DesignWave 2005 8 Verilog Example

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-- regI2cMaster (i2c Master Unit /w register I/F)
-- Takashi Kohno (DigiCat)
-- Rev. 0.5.0c  / 16, Jun., 2005
--
----------------------------------------
--
-- Copyright (c)   2005   Takashi Kohno
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or any later version.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
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library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;


entity regI2cMaster is
	generic( CKEDIVWIDTH		: integer := 4 ;
			 CKEDIV				: integer := 10
			 ) ;
	port(	CLK, nRST			: in std_logic ;
			
			-- Register I/F
			WrEn, RdEn			: in std_logic ;  -- Write Enable / Read Enable
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;  -- Address in the Unit
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;
			Int					: out std_logic ;  -- Interruption output (level drive)

			-- i2c bus
			SCL, SDA			: in std_logic ;
			mstSCL, mstSDA		: out std_logic
			) ;
end regI2cMaster ;



architecture RTL of regI2cMaster is

component rif_i2cMaster
	port(	CLK, nRST			: in std_logic ;
			CKE					: in std_logic ;  -- CLK enable for sampling clock
			
			-- Register I/F
			WrEn, RdEn			: in std_logic ;
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;
			Int					: out std_logic ;

			-- Local bus for slave functions
			syncRST				: out std_logic ;
			-- Transaction query
			MReq				: out std_logic ;
			Mi2cAdrs			: out std_logic_vector(6 downto 0) ;
			MRnW				: out std_logic ;
			MCont				: out std_logic ;
			MStB				: out std_logic ;
			MBusy				: in std_logic ;
			
			-- Master write stream
			MwrDReq				: in std_logic ;
			MwrData				: out std_logic_vector(7 downto 0) ;
			MwrTerm				: out std_logic ;
			MwrDRdy				: out std_logic ;
			
			-- Master read stream
			MrdDReq				: in std_logic ;
			MrdData				: in std_logic_vector(7 downto 0) ;
			MrdTerm				: out std_logic ;
			MrdDRdy				: out std_logic ;

			-- Status Reports
			srpBFree			: in std_logic ;
			srpBObsc			: in std_logic ;
			srpAdrs				: in std_logic ;
			srpWrite			: in std_logic ;
			srpArbt				: in std_logic ;
			srpAbort			: in std_logic ;

			-- Timing parameters
			Spre				: out std_logic_vector(3 downto 0) ;
			Spos				: out std_logic_vector(3 downto 0) ;
			Tlow				: out std_logic_vector(3 downto 0) ;
			Thig				: out std_logic_vector(3 downto 0) ;
			Dhol				: out std_logic_vector(1 downto 0)
			) ;
end component ;

component i2cMaster
	port(	CLK, nRST, syncRST	: in std_logic ;
			CKE					: in std_logic ;  -- CLK enable for sampling clock
			
			-- i2c bus
			SCL, SDA			: in std_logic ;
			mstSCL, mstSDA		: out std_logic ;

			-- Local bus for slave functions
			-- Transaction detection
			MReq				: in std_logic ;
			Mi2cAdrs			: in std_logic_vector(6 downto 0) ;
			MRnW				: in std_logic ;
			MCont				: in std_logic ;
			MStB				: in std_logic ;
			MBusy				: out std_logic ;
			
			-- Master write stream
			MwrDReq				: out std_logic ;
			MwrData				: in std_logic_vector(7 downto 0) ;
			MwrTerm				: in std_logic ;
			MwrDRdy				: in std_logic ;
			
			--Master read stream
			MrdDReq				: out std_logic ;
			MrdData				: out std_logic_vector(7 downto 0) ;
			MrdTerm				: in std_logic ;
			MrdDRdy				: in std_logic ;

			-- Status Reports
			srpBFree			: out std_logic ;
			srpBObsc			: out std_logic ;
			srpAdrs				: out std_logic ;
			srpWrite			: out std_logic ;
			srpArbt				: out std_logic ;
			srpAbort			: out std_logic ;

			-- Timing parameters
			Spre				: in std_logic_vector(3 downto 0) ;
			Spos				: in std_logic_vector(3 downto 0) ;
			Tlow				: in std_logic_vector(3 downto 0) ;
			Thig				: in std_logic_vector(3 downto 0) ;
			Dhol				: in std_logic_vector(1 downto 0)
			) ;
end component ;


-- connection signals
signal CKE				: std_logic ;  -- CLK enable for sampling clock
signal syncRST			: std_logic ;

signal MReq				: std_logic ;
signal Mi2cAdrs			: std_logic_vector(6 downto 0) ;
signal MRnW				: std_logic ;
signal MCont			: std_logic ;
signal MStB				: std_logic ;
signal MBusy			: std_logic ;
signal MwrDReq			: std_logic ;
signal MwrData			: std_logic_vector(7 downto 0) ;
signal MwrTerm			: std_logic ;
signal MwrDRdy			: std_logic ;
signal MrdDReq			: std_logic ;
signal MrdData			: std_logic_vector(7 downto 0) ;
signal MrdTerm			: std_logic ;
signal MrdDRdy			: std_logic ;
signal srpBFree			: std_logic ;
signal srpBObsc			: std_logic ;
signal srpAdrs			: std_logic ;
signal srpWrite			: std_logic ;
signal srpArbt			: std_logic ;
signal srpAbort			: std_logic ;
signal Spre				: std_logic_vector(3 downto 0) ;
signal Spos				: std_logic_vector(3 downto 0) ;
signal Tlow				: std_logic_vector(3 downto 0) ;
signal Thig				: std_logic_vector(3 downto 0) ;
signal Dhol				: std_logic_vector(1 downto 0) ;

-- CKE generator
signal CKECount					: std_logic_vector(CKEDIVWIDTH - 1 downto 0) ;


begin

-- component instantiation
	rifUNIT: rif_i2cMaster
		port map (	CLK => CLK, nRST => nRST,
					CKE => CKE,
					WrEn => WrEn, RdEn => RdEn,
					Usel => Usel,
					Uadrs => Uadrs,
					Din => Din,
					Dout => Dout,
					Int => Int,
					syncRST => syncRST,
					MReq => MReq,
					Mi2cAdrs => Mi2cAdrs,
					MRnW => MRnW,
					MCont => MCont,
					MStB => MStB,
					MBusy => MBusy,
					MwrDReq => MwrDReq,
					MwrData => MwrData,
					MwrTerm => MwrTerm,
					MwrDRdy => MwrDRdy,
					MrdDReq => MrdDReq,
					MrdData => MrdData,
					MrdTerm => MrdTerm,
					MrdDRdy => MrdDRdy,
					srpBFree => srpBFree,
					srpBObsc => srpBObsc,
					srpAdrs => srpAdrs,
					srpWrite => srpWrite,
					srpArbt => srpArbt,
					srpAbort => srpAbort,
					Spre => SPre,
					Spos => Spos,
					Tlow => Tlow,
					Thig => Thig,
					Dhol => Dhol
					) ;

	i2cMasterUNIT: i2cMaster
		port map (	CLK => CLK, nRST => nRST, syncRST => syncRST,
					CKE => CKE,
					SCL => SCL, SDA => SDA,
					mstSCL => mstSCL, mstSDA => mstSDA,
					MReq => MReq,
					Mi2cAdrs => Mi2cAdrs,
					MRnW => MRnW,
					MCont => MCont,
					MStB => MStB,
					MBusy => MBusy,
					MwrDReq => MwrDReq,
					MwrData => MwrData,
					MwrTerm => MwrTerm,
					MwrDRdy => MwrDRdy,
					MrdDReq => MrdDReq,
					MrdData => MrdData,
					MrdTerm => MrdTerm,
					MrdDRdy => MrdDRdy,
					srpBFree => srpBFree,
					srpBObsc => srpBObsc,
					srpAdrs => srpAdrs,
					srpWrite => srpWrite,
					srpArbt => srpArbt,
					srpAbort => srpAbort,
					Spre => Spre,
					Spos => Spos,
					Tlow => Tlow,
					Thig => Thig,
					Dhol => Dhol
					) ;



-- Clock Enable  Generation
	CKEGEN: process(CLK, nRST)
	begin
		if nRST = '0' then
			CKECount <= (others => '1') ;
		elsif rising_edge(CLK) then
			if CKE = '1' then
				CKECount <= CONV_STD_LOGIC_VECTOR(CKEDIV, CKEDIVWIDTH) ;
			else
				CKECount <= unsigned(CKECount) - 1 ;
			end if ;
		end if ;
	end process ;

	CKE <= '1' when CKECount = CONV_STD_LOGIC_VECTOR(0, CKEDIVWIDTH) else
		   '0' ;


end RTL ;