clk_divide_3.vhd

VHDL语言编写三分频

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY clk_divide_3 IS

	PORT
	(
		clkin ,rst: IN STD_LOGIC;
		clkout : OUT STD_LOGIC;
		t1,t2: out std_logic
		
	);


END clk_divide_3;


--  Architecture Body

ARCHITECTURE clk_divide_3_architecture OF clk_divide_3 IS
signal counter1,counter2 :integer range 0 to 3;
signal temp1,temp2: std_logic;

BEGIN
	process(rst,clkin)
	begin
		if rst='0' then
		if rising_edge(clkin) then
			if counter1=3 then
				counter1<=0;
				temp1<=not temp1;
			elsif counter1=2 then
				temp1<=not temp1;
				counter1<=counter1+1;
			else
				counter1<=counter1+1;
			end if;
		end if;
		
		if falling_edge(clkin) then
			if counter2=3 then
				counter2<=0;
				temp2<=not temp2;
			elsif counter2=2 then
				temp2<=not temp2;
				counter2<=counter2+1;
			else
				counter2<=counter2+1;
			end if;
		end if;	
		end if;	
	end process;
	t1<=temp1;
	t2<=temp2;	
	clkout<=temp1 and temp2;
	
END clk_divide_3_architecture;