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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity multi_clk_gen is
port(
clk110 : in vl_logic;
up150k : in vl_logic;
clk_main : out vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dec_syn is
port(
data_clk : in vl_logic;
reset : in vl_logic;
lost : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fifo_code is
port(
din : in vl_logic_vector(1 downto 0);
wr_en : in vl_logic;
wr_clk
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode34test_clk is
port(
add_cy_31_bit : in vl_logic_vector(30 downto 0);
clk110 : in vl_logic;
reset
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pn_catch is
port(
clk : in vl_logic;
reset : in vl_logic;
input_i : in vl_logic_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity data_source is
port(
data_clk : in vl_logic;
datain : out vl_logic;
reset : in vl_log
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode12_s is
port(
data_in : in vl_logic;
data_out_v : out vl_logic_vector(1 downto 0);
nd
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity transmitter2 is
generic(
IDLE : integer := 16;
STOP1 : integer := 10;
STOP2 : integer := 11
top_module_tb.v
//
// Verilog Module dwt_final_lib.top_module_tb.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 11:27:10 05/08/2008
//
// using Mentor Graphics HDL Designer(TM) 2004
collection.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter