top_module_tb.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.top_module_tb.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 11:27:10 05/08/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module top_module_tb ;

  reg clk,reset;
  reg [4:0] coeff;
  wire done;
  
  initial
  begin 
  clk=1'b0;
  reset=1'b0;
  coeff=5'b00011;
  #4 reset=1'b1;
  #3 reset=1'b0;
  #6 reset=1'b1;  
  end
  
  always
  #50 clk=!clk;
  
  Top_module  Tm(clk,reset,coeff,done);
  
 // ### Please start your Verilog code here ###
endmodule