_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity dec_syn is
    port(
        data_clk        : in     vl_logic;
        reset           : in     vl_logic;
        lost            : in     vl_logic;
        syn             : out    vl_logic;
        numb            : in     vl_logic_vector(11 downto 0)
    );
end dec_syn;