_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity max_min is
    generic(
        K               : integer := 8
    );
    port(
        reset           : in     vl_logic;
        data_clk        : in     vl_logic;
        shift_o         : out    vl_logic;
        s               : in     vl_logic_vector(9 downto 0);
        temp            : out    vl_logic_vector(15 downto 0);
        MAX             : out    vl_logic_vector(15 downto 0);
        catch           : out    vl_logic
    );
end max_min;