_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity data_source is
    port(
        data_clk        : in     vl_logic;
        datain          : out    vl_logic;
        reset           : in     vl_logic;
        datain_chi_370  : out    vl_logic;
        datain_chi_430  : out    vl_logic;
        datain_chi_470  : out    vl_logic
    );
end data_source;