_primary.vhd

简单的uart状态机的编写

library verilog;
use verilog.vl_types.all;
entity transmitter2 is
    generic(
        IDLE            : integer := 16;
        STOP1           : integer := 10;
        STOP2           : integer := 11;
        STOP3           : integer := 12;
        STOP4           : integer := 13;
        START1          : integer := 14;
        START2          : integer := 15;
        START           : integer := 1;
        DELAY1          : integer := 17;
        DELAY2          : integer := 18;
        DELAY3          : integer := 19;
        DELAY4          : integer := 20;
        D1              : integer := 1;
        D2              : integer := 2;
        D3              : integer := 3;
        D4              : integer := 4;
        D5              : integer := 5;
        D6              : integer := 6;
        D7              : integer := 7;
        D8              : integer := 8;
        PARITY          : integer := 9
    );
    port(
        in_clk          : in     vl_logic;
        in_resetn       : in     vl_logic;
        in_Data         : in     vl_logic_vector(7 downto 0);
        in_DataEnable   : in     vl_logic;
        out_NextData    : out    vl_logic;
        out_Bit         : out    vl_logic
    );
end transmitter2;