_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity pn_catch is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        input_i         : in     vl_logic_vector(2045 downto 0);
        input_q         : in     vl_logic_vector(2045 downto 0);
        reg_pn          : in     vl_logic_vector(1022 downto 0);
        catch           : out    vl_logic
    );
end pn_catch;