_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity fifo_code is
    port(
        din             : in     vl_logic_vector(1 downto 0);
        wr_en           : in     vl_logic;
        wr_clk          : in     vl_logic;
        rd_en           : in     vl_logic;
        rd_clk          : in     vl_logic;
        ainit           : in     vl_logic;
        dout            : out    vl_logic_vector(1 downto 0);
        full            : out    vl_logic;
        empty           : out    vl_logic;
        wr_count        : out    vl_logic_vector(1 downto 0)
    );
end fifo_code;