_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity encode34test_clk is
    port(
        add_cy_31_bit   : in     vl_logic_vector(30 downto 0);
        clk110          : in     vl_logic;
        reset           : in     vl_logic;
        data_clk        : out    vl_logic;
        data_i          : in     vl_logic;
        code_out34      : out    vl_logic;
        code_clk34      : out    vl_logic;
        qufan           : in     vl_logic
    );
end encode34test_clk;