代码搜索：Verilog

找到约 10,000 项符合「Verilog」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/415978/11046297

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity mt48lc8m16a2 is generic( addr_bits : integer := 12; data_bits : integer := 16; col_bits : integer := 9;
·
www.eeworm.com/read/267063/11196378

qmsg digtalclk.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
·
www.eeworm.com/read/248349/12581539

qmsg traffic.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
·
www.eeworm.com/read/248349/12581725

qmsg clock.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
·
www.eeworm.com/read/248342/12582120

qmsg div.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
·
www.eeworm.com/read/248071/12603744

exe unary_and.exe

function verilog_unary_and(val: Bit_Vector) return bit is variable result: bit ; begin result:=val(0); for i in 1 to (val'length-1) loop result := result and val(i); end loop;
·
www.eeworm.com/read/248071/12603757

exe unary_or.exe

function verilog_unary_or(val: Bit_Vector) return bit is variable result: bit ; begin result:=val(0); for i in 1 to (val'length-1) loop result := result or val(i); end loop; re
·
www.eeworm.com/read/334413/12604045

qmsg uart_clk.fit.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
·
www.eeworm.com/read/237764/13932657

qsf myadder.qsf

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
·
www.eeworm.com/read/235010/14088954

nlf ddr_command_timesim.nlf

Release 6.2i - netgen G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Loading device database for application netgen from file "ddr_command.ncd". "ddr_command" is an NCD, version 2
·