clock.map.qmsg

verilog HDL综合实验源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 14 14:45:09 2005 " "Info: Processing started: Wed Dec 14 14:45:09 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(18) " "Warning: Verilog HDL assignment warning at clock.v(18): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(19) " "Warning: Verilog HDL assignment warning at clock.v(19): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(20) " "Warning: Verilog HDL assignment warning at clock.v(20): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(21) " "Warning: Verilog HDL assignment warning at clock.v(21): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(22) " "Warning: Verilog HDL assignment warning at clock.v(22): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(23) " "Warning: Verilog HDL assignment warning at clock.v(23): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 clock.v(28) " "Warning: Verilog HDL assignment warning at clock.v(28): truncated value with size 32 to match size of target (16)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 28 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 clock.v(32) " "Warning: Verilog HDL assignment warning at clock.v(32): truncated value with size 32 to match size of target (16)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 clock.v(67) " "Warning: Verilog HDL assignment warning at clock.v(67): truncated value with size 32 to match size of target (26)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 clock.v(69) " "Warning: Verilog HDL assignment warning at clock.v(69): truncated value with size 32 to match size of target (26)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 69 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 clock.v(71) " "Warning: Verilog HDL assignment warning at clock.v(71): truncated value with size 32 to match size of target (26)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 71 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(77) " "Warning: Verilog HDL assignment warning at clock.v(77): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 77 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(78) " "Warning: Verilog HDL assignment warning at clock.v(78): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(79) " "Warning: Verilog HDL assignment warning at clock.v(79): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 79 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(80) " "Warning: Verilog HDL assignment warning at clock.v(80): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 80 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(81) " "Warning: Verilog HDL assignment warning at clock.v(81): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 81 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(82) " "Warning: Verilog HDL assignment warning at clock.v(82): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 82 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(83) " "Warning: Verilog HDL assignment warning at clock.v(83): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 83 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(84) " "Warning: Verilog HDL assignment warning at clock.v(84): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(89) " "Warning: Verilog HDL assignment warning at clock.v(89): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 89 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(91) " "Warning: Verilog HDL assignment warning at clock.v(91): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 91 0 0 } }  } 0}