unary_or.exe

將Verilog設計轉成VHDL設計的程式

function verilog_unary_or(val: Bit_Vector) 
	return bit is 
	variable result: bit ; 
	begin 
		result:=val(0); 
		for i in 1 to (val'length-1) loop 
				result := result or val(i); 
			end loop; 
		return result; 
	end verilog_unary_or;