traffic.map.qmsg

verilog HDL综合实验源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 14 14:42:43 2005 " "Info: Processing started: Wed Dec 14 14:42:43 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic" {  } {  } 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "24 traffic.v(45) " "Warning: (10229) Verilog HDL Expression warning at traffic.v(45): truncated literal to match 24 bits" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 45 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file traffic.v" { { "Info" "ISGN_ENTITY_NAME" "1 traffic " "Info: Found entity 1: traffic" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "traffic " "Info: Elaborating entity \"traffic\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 traffic.v(30) " "Warning: Verilog HDL assignment warning at traffic.v(30): truncated value with size 32 to match size of target (26)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 traffic.v(32) " "Warning: Verilog HDL assignment warning at traffic.v(32): truncated value with size 32 to match size of target (26)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 traffic.v(34) " "Warning: Verilog HDL assignment warning at traffic.v(34): truncated value with size 32 to match size of target (26)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(41) " "Warning: Verilog HDL assignment warning at traffic.v(41): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 41 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(42) " "Warning: Verilog HDL assignment warning at traffic.v(42): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(49) " "Warning: Verilog HDL assignment warning at traffic.v(49): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(52) " "Warning: Verilog HDL assignment warning at traffic.v(52): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 52 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(53) " "Warning: Verilog HDL assignment warning at traffic.v(53): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 53 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(57) " "Warning: Verilog HDL assignment warning at traffic.v(57): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 57 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(63) " "Warning: Verilog HDL assignment warning at traffic.v(63): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(66) " "Warning: Verilog HDL assignment warning at traffic.v(66): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(67) " "Warning: Verilog HDL assignment warning at traffic.v(67): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(71) " "Warning: Verilog HDL assignment warning at traffic.v(71): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 71 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(78) " "Warning: Verilog HDL assignment warning at traffic.v(78): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(79) " "Warning: Verilog HDL assignment warning at traffic.v(79): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 79 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(82) " "Warning: Verilog HDL assignment warning at traffic.v(82): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 82 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(86) " "Warning: Verilog HDL assignment warning at traffic.v(86): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.v" 86 0 0 } }  } 0}